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authorStefan Reinauer <stefan.reinauer@coreboot.org>2015-06-18 01:14:01 -0700
committerStefan Reinauer <stefan.reinauer@coreboot.org>2015-07-21 23:36:06 +0200
commit67b9430b367a9f9a884043f14365a55b7ef3c45c (patch)
tree950a1b04563c5471b256a95f10cdc5b9e70628b3 /src
parent29e6548ac2b720bdccf8367d2a663f128351df38 (diff)
downloadcoreboot-67b9430b367a9f9a884043f14365a55b7ef3c45c.tar.xz
cpu: port amd/agesa to 64bit
Change-Id: I8644b04f4b57db5fc95ec155d3f78d53c63c9831 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Signed-off-by: Scott Duplichan <scott@notabs.org> Reviewed-on: http://review.coreboot.org/10579 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Diffstat (limited to 'src')
-rw-r--r--src/cpu/amd/agesa/cache_as_ram.inc66
-rw-r--r--src/cpu/amd/agesa/s3_resume.c7
2 files changed, 71 insertions, 2 deletions
diff --git a/src/cpu/amd/agesa/cache_as_ram.inc b/src/cpu/amd/agesa/cache_as_ram.inc
index a8dbee8573..b19f03b0a6 100644
--- a/src/cpu/amd/agesa/cache_as_ram.inc
+++ b/src/cpu/amd/agesa/cache_as_ram.inc
@@ -64,9 +64,67 @@ cache_as_ram_setup:
cvtsi2sd %ebx, %xmm1
post_code(0xa1)
- AMD_ENABLE_STACK
- post_code(0xa1)
+#ifdef __x86_64__
+ /* switch to 64 bit long mode */
+ .intel_syntax noprefix
+
+ mov ecx, esi
+ add ecx, 0 # core number
+ xor eax, eax
+ lea edi, [ecx+0x1000+0x23]
+ mov dword ptr [ecx+0], edi
+ mov dword ptr [ecx+4], eax
+
+ lea edi, [ecx+0x1000]
+ mov dword ptr [edi+0x00], 0x000000e3
+ mov dword ptr [edi+0x04], eax
+ mov dword ptr [edi+0x08], 0x400000e3
+ mov dword ptr [edi+0x0c], eax
+ mov dword ptr [edi+0x10], 0x800000e3
+ mov dword ptr [edi+0x14], eax
+ mov dword ptr [edi+0x18], 0xc00000e3
+ mov dword ptr [edi+0x1c], eax
+
+ # load rom based identity mapped page tables
+ mov eax, ecx
+ mov cr3,eax
+
+ # enable PAE
+ mov eax, cr4
+ bts eax, 5
+ mov cr4, eax
+
+ # enable long mode
+ mov ecx, 0xC0000080
+ rdmsr
+ bts eax, 8
+ wrmsr
+
+ # enable paging
+ mov eax, cr0
+ bts eax, 31
+ mov cr0, eax
+
+ # use call far to switch to 64-bit code segment
+ jmp 0x18,.+7
+
+ /* Pass the BIST result */
+ cvtsd2si esi, xmm1
+
+ /* Pass the cpu_init_detected */
+ cvtsd2si edi, xmm0
+
+ /* align the stack */
+ and esp, 0xFFFFFFF0
+
+ .code64
+ call cache_as_ram_main
+ .code32
+
+ .att_syntax prefix
+#else
+ AMD_ENABLE_STACK
/* Restore the BIST result */
cvtsd2si %xmm0, %edx
@@ -77,6 +135,7 @@ cache_as_ram_setup:
pushl %ebx /* init detected */
pushl %edx /* bist */
call cache_as_ram_main
+#endif
/* Should never see this postcode */
post_code(0xaf)
@@ -108,3 +167,6 @@ disable_cache_as_ram:
ret
cache_as_ram_setup_out:
+#ifdef __x86_64__
+.code64
+#endif
diff --git a/src/cpu/amd/agesa/s3_resume.c b/src/cpu/amd/agesa/s3_resume.c
index 5e07d7a405..98671f47d5 100644
--- a/src/cpu/amd/agesa/s3_resume.c
+++ b/src/cpu/amd/agesa/s3_resume.c
@@ -56,10 +56,17 @@ static void move_stack_high_mem(void)
memcpy(high_stack, (void *)BSP_STACK_BASE_ADDR, HIGH_ROMSTAGE_STACK_SIZE);
/* TODO: We only switch stack on BSP. */
+#ifdef __x86_64__
+ __asm__
+ volatile ("add %0, %%rsp; add %0, %%rbp; invd"::"g"
+ (high_stack - BSP_STACK_BASE_ADDR)
+ :);
+#else
__asm__
volatile ("add %0, %%esp; add %0, %%ebp; invd"::"g"
(high_stack - BSP_STACK_BASE_ADDR)
:);
+#endif
}
static void set_resume_cache(void)