diff options
| author | Lijian Zhao <lijian.zhao@intel.com> | 2019-03-27 17:06:41 -0700 |
|---|---|---|
| committer | Duncan Laurie <dlaurie@chromium.org> | 2019-03-28 02:47:26 +0000 |
| commit | 68890b9d59d0f87533d3eacb6de1d552dcb72679 (patch) | |
| tree | 2b99cf49e67ad8c8f93cb9d84d5ea52a53cd410e /src | |
| parent | 39f9fbc57aeb60e65ec42d370d7ab76c0a4584d6 (diff) | |
| download | coreboot-68890b9d59d0f87533d3eacb6de1d552dcb72679.tar.xz | |
soc/intel/cannonlake: Update CPU Ratio base on MSR
The following is the FSP logic: as long as the Cpu Ratio input in
coreboot is different with CpuStrapSet, system will force to follow
input from coreboot. But CpuStrapsetting is floating, it will be 0
from the first cold boot before memory training and set to 0x1c (or
max CPU ratio for the installed CPU) after first memory training.
The previous fix was attempting to ensure settings were cleared
when FSP was called in recovery mode, but only when coming from S5
which caused issues if recovery mode is requested by the OS and
is only followed by a warm reset.
BUG=b:129412691
TEST=Boot up sarien platform and force recovery, check there's no reset
in the path of recovery.
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Change-Id: I959188be46343bc6f2cb3cc149097b4d449802aa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32089
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/intel/cannonlake/romstage/fsp_params.c | 19 |
1 files changed, 6 insertions, 13 deletions
diff --git a/src/soc/intel/cannonlake/romstage/fsp_params.c b/src/soc/intel/cannonlake/romstage/fsp_params.c index 3e3aa5e22a..ffdcee47e9 100644 --- a/src/soc/intel/cannonlake/romstage/fsp_params.c +++ b/src/soc/intel/cannonlake/romstage/fsp_params.c @@ -15,10 +15,12 @@ #include <assert.h> #include <chip.h> +#include <cpu/x86/msr.h> #include <console/console.h> #include <fsp/util.h> #include <intelblocks/pmclib.h> #include <soc/iomap.h> +#include <soc/msr.h> #include <soc/pci_devs.h> #include <soc/romstage.h> #include <vendorcode/google/chromeos/chromeos.h> @@ -69,19 +71,10 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, const config_t *config) m_cfg->SkipMpInit = !CONFIG_USE_INTEL_FSP_MP_INIT; #endif - /* Disable CPU Flex Ratio and SaGv in recovery mode */ - if (vboot_recovery_mode_enabled()) { - struct chipset_power_state *ps = pmc_get_power_state(); - - /* - * Only disable when coming from S5 (cold reset) otherwise - * the flex ratio may be locked and FSP will return an error. - */ - if (ps && ps->prev_sleep_state == ACPI_S5) { - m_cfg->CpuRatio = 0; - m_cfg->SaGv = 0; - } - } + /* Set CpuRatio to match existing MSR value */ + msr_t flex_ratio; + flex_ratio = rdmsr(MSR_FLEX_RATIO); + m_cfg->CpuRatio = (flex_ratio.lo >> 8) & 0xff; /* If ISH is enabled, enable ISH elements */ if (!dev) |