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authorElyes HAOUAS <ehaouas@noos.fr>2020-10-08 09:07:08 +0200
committerMichael Niewöhner <foss@mniewoehner.de>2021-01-28 21:31:49 +0000
commit693511033aa0eab08ea7f44ef710dcc2f590d408 (patch)
treed3589770d14e932ea4738b1e8bde19a2a0fbf0d5 /src
parent85a2026800f3d6e1994d69b860f0a08b85de2159 (diff)
downloadcoreboot-693511033aa0eab08ea7f44ef710dcc2f590d408.tar.xz
mb/amd/parmer: Convert to ASL 2.0 syntax
Change-Id: I563cd549858429049223677ebc503f9c9304baa0 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46149 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
-rw-r--r--src/mainboard/amd/parmer/acpi/sleep.asl16
1 files changed, 8 insertions, 8 deletions
diff --git a/src/mainboard/amd/parmer/acpi/sleep.asl b/src/mainboard/amd/parmer/acpi/sleep.asl
index dde9c37cd0..cd714cec87 100644
--- a/src/mainboard/amd/parmer/acpi/sleep.asl
+++ b/src/mainboard/amd/parmer/acpi/sleep.asl
@@ -26,20 +26,20 @@ Method(\_PTS, 1) {
/* DBGO("\n") */
/* Clear sleep SMI status flag and enable sleep SMI trap. */
- /*Store(One, CSSM)
- Store(One, SSEN)*/
+ /*CSSM = 1
+ SSEN = 1*/
/* On older chips, clear PciExpWakeDisEn */
- /*if (LLessEqual(\_SB.SBRI, 0x13)) {
- * Store(0,\_SB.PWDE)
+ /*if (\_SB.SBRI <= 0x13) {
+ * \_SB.PWDE = 0
*}
*/
/* Clear wake status structure. */
- Store(0, Index(WKST,0))
- Store(0, Index(WKST,1))
+ WKST [0] = 0
+ WKST [1] = 0
- Store (0x07, UPWS)
+ UPWS = 0x07
} /* End Method(\_PTS) */
/*
@@ -64,7 +64,7 @@ Method(\_WAK, 1) {
/* DBGO(" to S0\n") */
/* Re-enable HPET */
- Store(1,USBS)
+ USBS = 1
Return(WKST)
} /* End Method(\_WAK) */