siemens/mc_apl1: Make basic settings for booting the mainboard

This commit makes a basic adjustment for GPIOs, device tree, flash map and
MRC settings. With these basic settings the mainboard boots into
Linux lubuntu 4.8.0-22-generic using SeaBIOS. More adjustments will follow.

Change-Id: Ia920d236814f2e6a9b777dd1e4b4feef0ddf7721
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/18292
Tested-by: build bot (Jenkins)
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>

4 files changed, 93 insertions, 267 deletions

diff --git a/src/mainboard/siemens/mc_apl1/brd_gpio.h b/src/mainboard/siemens/mc_apl1/brd_gpio.h
index 33b839bbca..564ee69504 100644
--- a/src/mainboard/siemens/mc_apl1/brd_gpio.h
+++ b/src/mainboard/siemens/mc_apl1/brd_gpio.h
@@ -2,6 +2,7 @@
  * This file is part of the coreboot project.
  *
  * Copyright (C) 2015-2016 Intel Corporation. All Rights Reserved.
+ * Copyright (C) 2017 Siemens AG
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -18,11 +19,7 @@
 #if ENV_ROMSTAGE
 
 static const struct pad_config gpio_table[] = {
-	PAD_CFG_NF(GPIO_134, NATIVE, DEEP, NF2), /* ISH_I2C0_SDA/IO-OD */
-	PAD_CFG_NF(GPIO_135, NATIVE, DEEP, NF2), /* ISH_I2C0_SCL/IO-OD */
-	PAD_CFG_NF(GPIO_136, NATIVE, DEEP, NF2), /* ISH_I2C1_SDA/IO-OD */
-	PAD_CFG_NF(GPIO_137, NATIVE, DEEP, NF2), /* ISH_I2C1_SCL/IO-OD */
-
+	/* Debug tracing. */
 	PAD_CFG_NF(GPIO_0, NATIVE, DEEP, NF1),
 	PAD_CFG_NF(GPIO_1, NATIVE, DEEP, NF1),
 	PAD_CFG_NF(GPIO_2, NATIVE, DEEP, NF1),
@@ -33,30 +30,25 @@ static const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPIO_7, NATIVE, DEEP, NF1),
 	PAD_CFG_NF(GPIO_8, NATIVE, DEEP, NF1),
 
-	/* EXP_I2C_SDA and I2C_PSS_SDA and I2C_2_SDA_IOEXP */
-	PAD_CFG_NF(GPIO_7, NATIVE, DEEP, NF1),
-	/* EXP_I2C_SCL and I2C_PSS_SCL and I2C_2_SCL_IOEXP */
-	PAD_CFG_NF(GPIO_8, NATIVE, DEEP, NF1),
-
-	PAD_CFG_GPO(GPIO_152, 0, DEEP), /* PERST# */
-	PAD_CFG_GPO(GPIO_19, 1, DEEP), /* PFET */
-	PAD_CFG_GPO(GPIO_13, 0, DEEP), /* PERST# */
-	PAD_CFG_GPO(GPIO_17, 1, DEEP), /* PFET */
-	PAD_CFG_GPO(GPIO_15, 0, DEEP), /* PERST# */
+	PAD_CFG_GPI(GPIO_152, DN_20K, DEEP), /* Unused */
+	PAD_CFG_GPI(GPIO_19, UP_20K, DEEP), /* Unused */
+	PAD_CFG_GPI(GPIO_13, UP_20K, DEEP), /* Unused */
+	PAD_CFG_GPI(GPIO_17, UP_20K, DEEP), /* Unused */
+	PAD_CFG_GPI(GPIO_15, UP_20K, DEEP), /* Unused */
 
 	PAD_CFG_NF(GPIO_210, NATIVE, DEEP, NF1), /* CLKREQ# */
 
 	PAD_CFG_NF(SMB_CLK, NATIVE, DEEP, NF1),
 	PAD_CFG_NF(SMB_DATA, NATIVE, DEEP, NF1),
-	PAD_CFG_NF(LPC_ILB_SERIRQ, NATIVE, DEEP, NF1),
+	PAD_CFG_NF(LPC_ILB_SERIRQ, UP_20K, DEEP, NF1),
 	PAD_CFG_NF(LPC_CLKOUT0, NATIVE, DEEP, NF1),
-	PAD_CFG_NF(LPC_CLKOUT1, NATIVE, DEEP, NF1),
-	PAD_CFG_NF(LPC_AD0, NATIVE, DEEP, NF1),
-	PAD_CFG_NF(LPC_AD1, NATIVE, DEEP, NF1),
-	PAD_CFG_NF(LPC_AD2, NATIVE, DEEP, NF1),
-	PAD_CFG_NF(LPC_AD3, NATIVE, DEEP, NF1),
-	PAD_CFG_NF(LPC_CLKRUNB, NATIVE, DEEP, NF1),
-	PAD_CFG_NF(LPC_FRAMEB, NATIVE, DEEP, NF1),
+	PAD_CFG_GPI(LPC_CLKOUT1, UP_20K, DEEP), /* LPC_CLKOUT1 -- unused */
+	PAD_CFG_NF(LPC_AD0, UP_20K, DEEP, NF1),
+	PAD_CFG_NF(LPC_AD1, UP_20K, DEEP, NF1),
+	PAD_CFG_NF(LPC_AD2, UP_20K, DEEP, NF1),
+	PAD_CFG_NF(LPC_AD3, UP_20K, DEEP, NF1),
+	PAD_CFG_NF(LPC_CLKRUNB, UP_20K, DEEP, NF1),
+	PAD_CFG_NF(LPC_FRAMEB, UP_20K, DEEP, NF1),
 };
 
 #endif
diff --git a/src/mainboard/siemens/mc_apl1/devicetree.cb b/src/mainboard/siemens/mc_apl1/devicetree.cb
index ce01a8b82b..c82896c7fc 100644
--- a/src/mainboard/siemens/mc_apl1/devicetree.cb
+++ b/src/mainboard/siemens/mc_apl1/devicetree.cb
@@ -4,221 +4,54 @@ chip soc/intel/apollolake
 		device lapic 0 on end
 	end
 
-	register "pcie_rp0_clkreq_pin" = "0"    # wifi/bt
 	# Disable unused clkreq of PCIe root ports
+	register "pcie_rp0_clkreq_pin" = "3" # PCIe-PCI-Bridge
 	register "pcie_rp1_clkreq_pin" = "CLKREQ_DISABLED"
-	register "pcie_rp2_clkreq_pin" = "CLKREQ_DISABLED"
-	register "pcie_rp3_clkreq_pin" = "CLKREQ_DISABLED"
+	register "pcie_rp2_clkreq_pin" = "0" # MACPHY
+	register "pcie_rp3_clkreq_pin" = "1" # MACPHY
 	register "pcie_rp4_clkreq_pin" = "CLKREQ_DISABLED"
 	register "pcie_rp5_clkreq_pin" = "CLKREQ_DISABLED"
 
-	# GPIO for PERST_0
-	# If the Board has PERST_0 signal, assign the GPIO
-	# If the Board does not have PERST_0, assign GPIO_PRT0_UDEF
-	register "prt0_gpio" = "GPIO_122"
-
-	# EMMC TX DATA Delay 1
-	# Refer to EDS-Vol2-22.3.
-	# [14:8] steps of delay for HS400, each 125ps.
-	# [6:0] steps of delay for SDR104/HS200, each 125ps.
-	register "emmc_tx_data_cntl1" = "0x0C16"
-
-	# EMMC TX DATA Delay 2
-	# Refer to EDS-Vol2-22.3.
-	# [30:24] steps of delay for SDR50, each 125ps.
-	# [22:16] steps of delay for DDR50, each 125ps.
-	# [14:8] steps of delay for SDR25/HS50, each 125ps.
-	# [6:0] steps of delay for SDR12, each 125ps.
-	register "emmc_tx_data_cntl2" = "0x28162828"
-
-	# EMMC RX CMD/DATA Delay 1
-	# Refer to EDS-Vol2-22.3.
-	# [30:24] steps of delay for SDR50, each 125ps.
-	# [22:16] steps of delay for DDR50, each 125ps.
-	# [14:8] steps of delay for SDR25/HS50, each 125ps.
-	# [6:0] steps of delay for SDR12, each 125ps.
-	register "emmc_rx_cmd_data_cntl1" = "0x00181717"
-
-	# EMMC RX CMD/DATA Delay 2
-	# Refer to EDS-Vol2-22.3.
-	# [17:16] stands for Rx Clock before Output Buffer
-	# [14:8] steps of delay for Auto Tuning Mode, each 125ps.
-	# [6:0] steps of delay for HS200, each 125ps.
-	register "emmc_rx_cmd_data_cntl2" = "0x10008"
-
-	# Enable DPTF
-	register "dptf_enable" = "1"
-
-	# PL1 override 12000 mW: the energy calculation is wrong with the
-	# current VR solution. Experiments show that SoC TDP max (6W) can
-	# be reached when RAPL PL1 is set to 12W.
-	register "tdp_pl1_override_mw" = "12000"
-	# Set RAPL PL2 to 15W.
-	register "tdp_pl2_override_mw" = "15000"
-
-	# Enable Audio Clock and Power gating
-	register "hdaudio_clk_gate_enable" = "1"
-	register "hdaudio_pwr_gate_enable" = "1"
-	register "hdaudio_bios_config_lockdown" = "1"
-
-	# Enable lpss s0ix
-	register "lpss_s0ix_enable" = "1"
-
-	# GPE configuration
-	# Note that GPE events called out in ASL code rely on this
-	# route, i.e., if this route changes then the affected GPE
-	# offset bits also need to be changed. This sets the PMC register
-	# GPE_CFG fields.
-	register "gpe0_dw1" = "PMC_GPE_N_31_0"
-	register "gpe0_dw2" = "PMC_GPE_N_63_32"
-	register "gpe0_dw3" = "PMC_GPE_SW_31_0"
-
-	# Enable I2C0 for audio codec at 400kHz
-	register "i2c[0]" = "{
-		.speed = I2C_SPEED_FAST,
-		.rise_time_ns = 104,
-		.fall_time_ns = 52,
-	}"
-
-	# Enable I2C2 bus early for TPM at 400kHz
-	register "i2c[2]" = "{
-		.early_init = 1,
-		.speed = I2C_SPEED_FAST,
-		.rise_time_ns = 57,
-		.fall_time_ns = 28,
-	}"
-
-	# touchscreen at 400kHz
-	register "i2c[3]" = "{
-		.speed = I2C_SPEED_FAST,
-		.rise_time_ns = 76,
-		.fall_time_ns = 164,
-	}"
-
-	# trackpad at 400kHz
-	register "i2c[4]" = "{
-		.speed = I2C_SPEED_FAST,
-		.rise_time_ns = 114,
-		.fall_time_ns = 164,
-	}"
-
-	# digitizer at 400kHz
-	register "i2c[5]" = "{
-		.speed = I2C_SPEED_FAST,
-		.rise_time_ns = 152,
-		.fall_time_ns = 30,
-	}"
-
-	# Minimum SLP S3 assertion width 28ms.
-	register "slp_s3_assertion_width_usecs" = "28000"
-
 	device domain 0 on
 		device pci 00.0 on  end	# - Host Bridge
-		device pci 00.1 on  end	# - DPTF
-		device pci 00.2 on  end	# - NPK
-		device pci 02.0 on  end	# - Gen
-		device pci 03.0 on  end	# - Iunit
+		device pci 00.1 off end	# - DPTF
+		device pci 00.2 off end	# - NPK
+		device pci 02.0 on  end	# - Gen - Display
+		device pci 03.0 off end	# - Iunit
 		device pci 0d.0 on  end	# - P2SB
-		device pci 0d.1 on  end	# - PMC
+		device pci 0d.1 off end	# - PMC
 		device pci 0d.2 on  end	# - SPI
-		device pci 0d.3 on  end	# - Shared SRAM
-		device pci 0e.0 on	# - Audio
-			chip drivers/generic/max98357a
-				register "sdmode_gpio" =  "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_76)"
-				register "sdmode_delay" = "5"
-				device generic 0 on end
-			end
-		end
-		device pci 11.0 off end	# - ISH
-		device pci 12.0 off end	# - SATA
-		device pci 13.0 off end	# - Root Port 2 - PCIe-A 0
-		device pci 13.1 off end	# - Root Port 3 - PCIe-A 1
-		device pci 13.2 off end	# - Root Port 4 - PCIe-A 2
-		device pci 13.3 off end	# - Root Port 5 - PCIe-A 3
-		device pci 14.0 on
-			chip drivers/intel/wifi
-				register "wake" = "GPE0_DW3_00"
-				device pci 00.0 on end
-			end
-		end	# - Root Port 0 - PCIe-B 0 - Wifi
-		device pci 14.1 off end	# - Root Port 1 - PCIe-B 1
+		device pci 0d.3 off end	# - Shared SRAM
+		device pci 0e.0 off end	# - Audio
+		device pci 11.0 on  end	# - ISH
+		device pci 12.0 on  end	# - SATA
+		device pci 13.0 on  end	# - RP 2 - PCIe A 0 - MACPHY
+		device pci 13.1 on  end	# - RP 3 - PCIe A 1 - MACPHY
+		device pci 13.2 off end	# - RP 4 - PCIe-A 2
+		device pci 13.3 off end	# - RP 5 - PCIe-A 3
+		device pci 14.0 on  end	# - RP 0 - PCIe-B 0 - PCIe-PCI-Bridge
+		device pci 14.1 off end	# - RP 1 - PCIe-B 1
 		device pci 15.0 on  end	# - XHCI
-		device pci 15.1 off end # - XDCI
-		device pci 16.0 on	# - I2C 0
-			chip drivers/i2c/da7219
-				register "irq" = "IRQ_LEVEL_LOW(GPIO_116_IRQ)"
-				register "btn_cfg" = "50"
-				register "mic_det_thr" = "500"
-				register "jack_ins_deb" = "20"
-				register "jack_det_rate" = ""32ms_64ms""
-				register "jack_rem_deb" = "1"
-				register "a_d_btn_thr" = "0xa"
-				register "d_b_btn_thr" = "0x16"
-				register "b_c_btn_thr" = "0x21"
-				register "c_mic_btn_thr" = "0x3e"
-				register "btn_avg" = "4"
-				register "adc_1bit_rpt" = "1"
-				register "micbias_lvl" = "2600"
-				register "mic_amp_in_sel" = ""diff""
-				device i2c 1a on end
-			end
-		end
-		device pci 16.1 on  end	# - I2C 1
-		device pci 16.2 on
-			chip drivers/i2c/tpm
-				register "hid" = ""GOOG0005""
-				register "irq" = "IRQ_EDGE_LOW(GPIO_28_IRQ)"
-				device i2c 50 on end
-			end
-		end	# - I2C 2
-		device pci 16.3 on
-			chip drivers/i2c/generic
-				register "hid" = ""ELAN0001""
-				register "desc" = ""ELAN Touchscreen""
-				register "irq" = "IRQ_EDGE_LOW(GPIO_21_IRQ)"
-				register "probed" = "1"
-				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_36)"
-				register "reset_delay_ms" = "20"
-				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_152)"
-				register "enable_delay_ms" = "1"
-				register "has_power_resource" = "1"
-				device i2c 10 on end
-			end
-		end	# - I2C 3
-		device pci 17.0 on
-			chip drivers/i2c/generic
-				register "hid" = ""ELAN0000""
-				register "desc" = ""ELAN Touchpad""
-				register "irq" = "IRQ_EDGE_LOW(GPIO_18_IRQ)"
-				register "wake" = "GPE0_DW1_15"
-				register "probed" = "1"
-				device i2c 15 on end
-			end
-		end # - I2C 4
-		device pci 17.1 on
-			chip drivers/i2c/wacom
-				register "generic" = "{
-					 .hid = WCOM50C1_HID,
-					 .cid = PNP0C50_CID,
-					 .desc = WCOM_DT_DESC,
-					 .irq = IRQ_LEVEL_LOW(GPIO_13_IRQ),
-				}"
-				register "hid_desc_reg_offset" = "0x1"
-				device i2c 0x9 on end
-			end
-		end	# - I2C 5
+		device pci 15.1 on  end	# - XDCI
+		device pci 16.0 on  end	# - I2C 0
+		device pci 16.1 off end	# - I2C 1
+		device pci 16.2 off end	# - I2C 2
+		device pci 16.3 off end	# - I2C 3
+		device pci 17.0 off end	# - I2C 4
+		device pci 17.1 off end	# - I2C 5
 		device pci 17.2 off end	# - I2C 6
-		device pci 17.3 off end	# - I2C 7
+		device pci 17.3 on  end	# - I2C 7
 		device pci 18.0 on  end	# - UART 0
 		device pci 18.1 on  end	# - UART 1
 		device pci 18.2 on  end	# - UART 2
-		device pci 18.3 off end	# - UART 3
-		device pci 19.0 on  end	# - SPI 0
+		device pci 18.3 on  end	# - UART 3
+		device pci 19.0 off end	# - SPI 0
 		device pci 19.1 off end	# - SPI 1
 		device pci 19.2 off end	# - SPI 2
-		device pci 1a.0 on  end	# - PWM
+		device pci 1a.0 off end	# - PWM
 		device pci 1b.0 on  end	# - SDCARD
 		device pci 1c.0 on  end	# - eMMC
+		device pci 1d.0 off end	# - UFS
 		device pci 1e.0 off end	# - SDIO
 		device pci 1f.0 on  end	# - LPC
 		device pci 1f.1 on  end	# - SMBUS
diff --git a/src/mainboard/siemens/mc_apl1/mc_apl1.fmd b/src/mainboard/siemens/mc_apl1/mc_apl1.fmd
index 3da8467431..432e8de284 100644
--- a/src/mainboard/siemens/mc_apl1/mc_apl1.fmd
+++ b/src/mainboard/siemens/mc_apl1/mc_apl1.fmd
@@ -1,15 +1,16 @@
 FLASH 16M {
-	WP_RO@0x0 0x400000 {
+	WP_RO@0x0 0xe00000 {
 		SI_DESC@0x0 0x1000
-		IFWI@0x1000 0x1ff000
-		RO_VPD@0x200000 0x4000
-		RO_SECTION@0x204000 0x1fc000 {
+		IFWI@0x1000 0x23f000
+		RO_VPD@0x240000 0x4000
+		RO_SECTION@0x244000 0xbbc000 {
 			FMAP@0x0 0x800
-			COREBOOT(CBFS)@0x1000 0x1bb000
-			RO_UNUSED@0x1bc000 0x40000
+			RO_UNUSED_1@0x800 0x800
+			COREBOOT(CBFS)@0x1000 0xbb9000
+			RO_UNUSED_2@0xbba000 0x1000
 		}
 	}
-	MISC_RW@0x400000 0x30000 {
+	MISC_RW@0xe00000 0x30000 {
 		UNIFIED_MRC_CACHE@0x0 0x21000 {
 			RECOVERY_MRC_CACHE@0x0 0x10000
 			RW_MRC_CACHE@0x10000 0x10000
@@ -23,9 +24,8 @@ FLASH 16M {
 		RW_VPD@0x28000 0x2000
 		RW_NVRAM@0x2a000 0x6000
 	}
-	RW_LEGACY(CBFS)@0xd30000 0x200000
-	BIOS_UNUSABLE@0xf30000 0x4f000
-	DEVICE_EXTENSION@0xf7f000 0x80000
+	BIOS_UNUSABLE@0xe30000 0xcf000
+	DEVICE_EXTENSION@0xeff000 0x100000
 	# Currently, it is required that the BIOS region be a multiple of 8KiB.
 	# This is required so that the recovery mechanism can find SIGN_CSE
 	# region aligned to 4K at the center of BIOS region. Since the
diff --git a/src/mainboard/siemens/mc_apl1/romstage.c b/src/mainboard/siemens/mc_apl1/romstage.c
index 5c784ba629..9dd42bcfec 100644
--- a/src/mainboard/siemens/mc_apl1/romstage.c
+++ b/src/mainboard/siemens/mc_apl1/romstage.c
@@ -2,6 +2,7 @@
  * This file is part of the coreboot project.
  *
  * Copyright 2016 Google Inc.
+ * Copyright (C) 2017 Siemens AG
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -20,28 +21,28 @@
 #include "brd_gpio.h"
 
 static const uint8_t Ch0_Bit_swizzling[] = {
-	0x09, 0x0e, 0x0c, 0x0d, 0x0a, 0x0b, 0x08, 0x0f,
-	0x05, 0x06, 0x01, 0x00, 0x02, 0x07, 0x04, 0x03,
-	0x1a, 0x1f, 0x1c, 0x1b, 0x1d, 0x19, 0x18, 0x1e,
-	0x14, 0x16, 0x17, 0x11, 0x12, 0x13, 0x10, 0x15
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
 };
 static const uint8_t Ch1_Bit_swizzling[] = {
-	0x06, 0x07, 0x05, 0x04, 0x03, 0x01, 0x00, 0x02,
-	0x0c, 0x0a, 0x0b, 0x0d, 0x0e, 0x08, 0x09, 0x0f,
-	0x14, 0x10, 0x16, 0x15, 0x12, 0x11, 0x13, 0x17,
-	0x1e, 0x1c, 0x1d, 0x19, 0x18, 0x1a, 0x1b, 0x1f
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
 };
 static const uint8_t Ch2_Bit_swizzling[] = {
-	0x0f, 0x09, 0x08, 0x0b, 0x0c, 0x0d, 0x0e, 0x0a,
-	0x05, 0x02, 0x00, 0x03, 0x06, 0x07, 0x01, 0x04,
-	0x19, 0x1c, 0x1e, 0x1f, 0x1a, 0x1b, 0x18, 0x1d,
-	0x14, 0x17, 0x16, 0x15, 0x12, 0x13, 0x10, 0x11
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
 };
 static const uint8_t Ch3_Bit_swizzling[] = {
-	0x03, 0x04, 0x06, 0x05, 0x00, 0x01, 0x02, 0x07,
-	0x0b, 0x0a, 0x08, 0x09, 0x0e, 0x0c, 0x0f, 0x0d,
-	0x11, 0x17, 0x13, 0x10, 0x15, 0x16, 0x14, 0x12,
-	0x1c, 0x1d, 0x1a, 0x19, 0x1e, 0x1b, 0x18, 0x1f
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
 };
 
 void mainboard_memory_init_params(FSPM_UPD *memupd)
@@ -51,59 +52,59 @@ void mainboard_memory_init_params(FSPM_UPD *memupd)
 
 	/* DRAM Config settings */
 	memupd->FspmConfig.Package = 0x1;
-	memupd->FspmConfig.Profile = 0xB;
+	memupd->FspmConfig.Profile = 0x19;
 	memupd->FspmConfig.MemoryDown = 0x1;
-	memupd->FspmConfig.DDR3LPageSize = 0x0;
+	memupd->FspmConfig.DDR3LPageSize = 0x2;
 	memupd->FspmConfig.DDR3LASR = 0x0;
-	memupd->FspmConfig.ScramblerSupport = 0x1;
-	memupd->FspmConfig.ChannelHashMask = 0x36;
-	memupd->FspmConfig.SliceHashMask = 0x9;
-	memupd->FspmConfig.InterleavedMode = 0x2;
+	memupd->FspmConfig.ScramblerSupport = 0x0;
+	memupd->FspmConfig.ChannelHashMask = 0x0;
+	memupd->FspmConfig.SliceHashMask = 0x0;
+	memupd->FspmConfig.InterleavedMode = 0x0;
 	memupd->FspmConfig.ChannelsSlicesEnable = 0x0;
-	memupd->FspmConfig.MinRefRate2xEnable = 0x0;
+	memupd->FspmConfig.MinRefRate2xEnable = 0x1;
 	memupd->FspmConfig.DualRankSupportEnable = 0x1;
 	memupd->FspmConfig.RmtMode = 0x0;
-	memupd->FspmConfig.MemorySizeLimit = 0x1800;
+	memupd->FspmConfig.MemorySizeLimit = 0x1000;
 	memupd->FspmConfig.LowMemoryMaxValue = 0x0;
 	memupd->FspmConfig.DisableFastBoot = 0x0;
 	memupd->FspmConfig.HighMemoryMaxValue = 0x0;
 	memupd->FspmConfig.DIMM0SPDAddress = 0x0;
 	memupd->FspmConfig.DIMM1SPDAddress = 0x0;
-	memupd->FspmConfig.Ch0_RankEnable = 0x3;
+	memupd->FspmConfig.Ch0_RankEnable = 0x1;
 	memupd->FspmConfig.Ch0_DeviceWidth = 0x1;
-	memupd->FspmConfig.Ch0_DramDensity = 0x2;
+	memupd->FspmConfig.Ch0_DramDensity = 0x0;
 	memupd->FspmConfig.Ch0_Option = 0x3;
-	memupd->FspmConfig.Ch0_OdtConfig = 0x0;
+	memupd->FspmConfig.Ch0_OdtConfig = 0x1;
 	memupd->FspmConfig.Ch0_TristateClk1 = 0x0;
 	memupd->FspmConfig.Ch0_Mode2N = 0x0;
 	memupd->FspmConfig.Ch0_OdtLevels = 0x0;
-	memupd->FspmConfig.Ch1_RankEnable = 0x3;
+	memupd->FspmConfig.Ch1_RankEnable = 0x1;
 	memupd->FspmConfig.Ch1_DeviceWidth = 0x1;
-	memupd->FspmConfig.Ch1_DramDensity = 0x2;
+	memupd->FspmConfig.Ch1_DramDensity = 0x0;
 	memupd->FspmConfig.Ch1_Option = 0x3;
-	memupd->FspmConfig.Ch1_OdtConfig = 0x0;
+	memupd->FspmConfig.Ch1_OdtConfig = 0x1;
 	memupd->FspmConfig.Ch1_TristateClk1 = 0x0;
 	memupd->FspmConfig.Ch1_Mode2N = 0x0;
 	memupd->FspmConfig.Ch1_OdtLevels = 0x0;
-	memupd->FspmConfig.Ch2_RankEnable = 0x3;
+	memupd->FspmConfig.Ch2_RankEnable = 0x0;
 	memupd->FspmConfig.Ch2_DeviceWidth = 0x1;
-	memupd->FspmConfig.Ch2_DramDensity = 0x2;
+	memupd->FspmConfig.Ch2_DramDensity = 0x0;
 	memupd->FspmConfig.Ch2_Option = 0x3;
 	memupd->FspmConfig.Ch2_OdtConfig = 0x0;
 	memupd->FspmConfig.Ch2_TristateClk1 = 0x0;
 	memupd->FspmConfig.Ch2_Mode2N = 0x0;
 	memupd->FspmConfig.Ch2_OdtLevels = 0x0;
-	memupd->FspmConfig.Ch3_RankEnable = 0x3;
+	memupd->FspmConfig.Ch3_RankEnable = 0x0;
 	memupd->FspmConfig.Ch3_DeviceWidth = 0x1;
-	memupd->FspmConfig.Ch3_DramDensity = 0x2;
+	memupd->FspmConfig.Ch3_DramDensity = 0x0;
 	memupd->FspmConfig.Ch3_Option = 0x3;
 	memupd->FspmConfig.Ch3_OdtConfig = 0x0;
 	memupd->FspmConfig.Ch3_TristateClk1 = 0x0;
 	memupd->FspmConfig.Ch3_Mode2N = 0x0;
 	memupd->FspmConfig.Ch3_OdtLevels = 0x0;
-	memupd->FspmConfig.RmtCheckRun = 0x0;
+	memupd->FspmConfig.RmtCheckRun = 0x3;
 	memupd->FspmConfig.MrcDataSaving = 0x0;
-	memupd->FspmConfig.MrcFastBoot   = 0x0;
+	memupd->FspmConfig.MrcFastBoot   = 0x1;
 
 	memcpy(memupd->FspmConfig.Ch0_Bit_swizzling, &Ch0_Bit_swizzling,
 		sizeof(Ch0_Bit_swizzling));
@@ -114,6 +115,6 @@ void mainboard_memory_init_params(FSPM_UPD *memupd)
 	memcpy(memupd->FspmConfig.Ch3_Bit_swizzling, &Ch3_Bit_swizzling,
 		sizeof(Ch3_Bit_swizzling));
 
-	memupd->FspmConfig.RmtMarginCheckScaleHighThreshold = 0x0;
+	memupd->FspmConfig.RmtMarginCheckScaleHighThreshold = 0xC8;
 	memupd->FspmConfig.MsgLevelMask = 0x0;
 }