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| author | Hannah Williams <hannah.williams@intel.com> | 2016-06-02 15:00:36 -0700 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-07-07 17:02:57 +0200 |
| commit | 7124882aeb45ed863c12dcd9cea2f3ab033b2ee4 (patch) | |
| tree | c97e672517cdfce859e40101429cd41a66ce1b1b /src | |
| parent | e1d6aa6e4195f5fce6cb65d39d36289e6786fa36 (diff) | |
| download | coreboot-7124882aeb45ed863c12dcd9cea2f3ab033b2ee4.tar.xz | |
board/intel/amenia: Enable LPSS S0ix
This setting will enable S0ix for LPSS
Change-Id: Ie07cb8437d0cee61a03638aa980fd3322fef0c4e
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-on: https://review.coreboot.org/15056
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src')
| -rw-r--r-- | src/mainboard/intel/amenia/devicetree.cb | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/mainboard/intel/amenia/devicetree.cb b/src/mainboard/intel/amenia/devicetree.cb index 2080d6f769..7045f59b5d 100644 --- a/src/mainboard/intel/amenia/devicetree.cb +++ b/src/mainboard/intel/amenia/devicetree.cb @@ -15,6 +15,9 @@ chip soc/intel/apollolake # 0x1A[6:0] stands for 26*125 = 3250 pSec delay for SDR104/HS200 register "emmc_tx_data_cntl1" = "0x1A1A" # HS400 required + # LPSS S0ix Enable + register "lpss_s0ix_enable" = "1" + device domain 0 on device pci 00.0 on end # - Host Bridge device pci 00.1 on end # - DPTF |