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| author | Edward O'Callaghan <quasisec@google.com> | 2019-12-30 19:27:53 +1100 |
|---|---|---|
| committer | Edward O'Callaghan <quasisec@chromium.org> | 2020-01-02 04:18:28 +0000 |
| commit | 731e6288e6f6117951ca407a651e25f346843621 (patch) | |
| tree | 4674415a138da20dc6270bd4c21c30141a6b9b94 /src | |
| parent | ef4fe3e37c2741bec14b42ab37cddaa91342d232 (diff) | |
| download | coreboot-731e6288e6f6117951ca407a651e25f346843621.tar.xz | |
mainboard/google/puff: Enable net driver on pcie ep
Let coreboot know there is a NIC device on the end so
that the mac from vpd is set at early boot.
Properly configure the link-leds in devicetree s.t.
valid values are written out to the register at initialization.
BUG=b:146592075,146999042,146999043
BRANCH=none
TEST=Boot to kernel.
Insert mac address into VPD
vpd -s ethernet_mac=<address>
reboot the system.
Ensure we have ip address and corresponding mac
address with ifconfig.
Ensure ethernet controller shows up with lspci.
Change-Id: I76ce6d8a5a26842fcb2544ee96567fe0da8603b1
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38003
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Daniel Kurtz <djkurtz@google.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/mainboard/google/hatch/variants/puff/overridetree.cb | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/src/mainboard/google/hatch/variants/puff/overridetree.cb b/src/mainboard/google/hatch/variants/puff/overridetree.cb index 342994d90a..4385e981b8 100644 --- a/src/mainboard/google/hatch/variants/puff/overridetree.cb +++ b/src/mainboard/google/hatch/variants/puff/overridetree.cb @@ -179,7 +179,12 @@ chip soc/intel/cannonlake end end #I2C #4 device pci 1a.0 on end # eMMC - device pci 1c.0 on end # FSP requires func0 be enabled. + device pci 1c.0 on + chip drivers/net + register "customized_leds" = "0x05af" + device pci 00.0 on end + end + end # FSP requires func0 be enabled. device pci 1c.6 on end # RTL8111H Ethernet NIC (becomes RP1). device pci 1e.3 off end # GSPI #1 end |