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authorSubrata Banik <subrata.banik@intel.com>2020-09-28 21:03:27 +0530
committerSubrata Banik <subrata.banik@intel.com>2020-09-30 03:54:29 +0000
commit7335225600e5031760e4e0f5f20b2b49e4ac6a95 (patch)
tree2cb6bf759037e7f3e4d3cf16a839868aa7792e6e /src
parent063e933194ec9b41775f5e2f1a175f1c97657f1b (diff)
downloadcoreboot-7335225600e5031760e4e0f5f20b2b49e4ac6a95.tar.xz
soc/intel/skylake: Move PMC MMIO offset macro into pmc.h
This patch ensures PMC offset 0xfc resides into pmc.h rather defining into p2sb.h. Change-Id: Iae1c38beae15355a077be80112b723b8ad3d0a44 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45800 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
-rw-r--r--src/soc/intel/skylake/include/soc/p2sb.h2
-rw-r--r--src/soc/intel/skylake/include/soc/pmc.h1
2 files changed, 1 insertions, 2 deletions
diff --git a/src/soc/intel/skylake/include/soc/p2sb.h b/src/soc/intel/skylake/include/soc/p2sb.h
index 940ea13c96..41654e70da 100644
--- a/src/soc/intel/skylake/include/soc/p2sb.h
+++ b/src/soc/intel/skylake/include/soc/p2sb.h
@@ -11,6 +11,4 @@
#define PCH_P2SB_EPMASK0 0xB0
-#define PCH_PWRM_ACPI_TMR_CTL 0xFC
-
#endif /* _SOC_P2SB_H_ */
diff --git a/src/soc/intel/skylake/include/soc/pmc.h b/src/soc/intel/skylake/include/soc/pmc.h
index 68d9eb3d27..6d52b9dbc5 100644
--- a/src/soc/intel/skylake/include/soc/pmc.h
+++ b/src/soc/intel/skylake/include/soc/pmc.h
@@ -77,6 +77,7 @@
#define DSX_EN_LAN_WAKE_PIN (1 << 0)
#define PMSYNC_TPR_CFG 0xc4
#define PMSYNC_LOCK (1 << 31)
+#define PCH_PWRM_ACPI_TMR_CTL 0xfc
#define GPIO_GPE_CFG 0x120
#define GPE0_DWX_MASK 0xf
#define GPE0_DW_SHIFT(x) (4*(x))