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| author | John Zhao <john.zhao@intel.com> | 2020-05-13 15:40:07 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-05-18 07:34:08 +0000 |
| commit | 7a05e6e2ad75dc1e28a50f3f309d8e7aecaf2526 (patch) | |
| tree | 419240764873aca2adff99689a764b1cec84c39c /src | |
| parent | d7b9e363e3ec09eb5e2977d16085fdb3cd1334ce (diff) | |
| download | coreboot-7a05e6e2ad75dc1e28a50f3f309d8e7aecaf2526.tar.xz | |
soc/intel/tigerlake: Add FSP UPD TcssDma0En and TcssDma1En
This adds FSP UPD TcssDma0En and TcssDma1En for configuration.
BUG=:b:146624360
TEST=Built and booted on Volteer.
Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: I04af970f74ab9dfe84f9c0c09ec2098e0093fa57
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41383
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/intel/tigerlake/chip.h | 6 | ||||
| -rw-r--r-- | src/soc/intel/tigerlake/include/soc/pci_devs.h | 16 | ||||
| -rw-r--r-- | src/soc/intel/tigerlake/romstage/fsp_params.c | 6 |
3 files changed, 23 insertions, 5 deletions
diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h index c98fb667cc..3047037183 100644 --- a/src/soc/intel/tigerlake/chip.h +++ b/src/soc/intel/tigerlake/chip.h @@ -213,10 +213,14 @@ struct soc_intel_tigerlake_config { FORCE_ENABLE, } CnviBtAudioOffload; - /* Tcss */ + /* Tcss USB */ uint8_t TcssXhciEn; uint8_t TcssXdciEn; + /* Tcss DMA */ + uint8_t TcssDma0En; + uint8_t TcssDma1En; + /* * SOC Aux orientation override: * This is a bitfield that corresponds to up to 4 TCSS ports on TGL. diff --git a/src/soc/intel/tigerlake/include/soc/pci_devs.h b/src/soc/intel/tigerlake/include/soc/pci_devs.h index 683172f346..d76c4a105b 100644 --- a/src/soc/intel/tigerlake/include/soc/pci_devs.h +++ b/src/soc/intel/tigerlake/include/soc/pci_devs.h @@ -30,6 +30,10 @@ #define SA_DEVFN_DPTF PCI_DEVFN(SA_DEV_SLOT_DPTF, 0) #define SA_DEV_DPTF PCI_DEV(0, SA_DEV_SLOT_DPTF, 0) +#define SA_DEV_SLOT_IPU 0x05 +#define SA_DEVFN_IPU PCI_DEVFN(SA_DEV_SLOT_IPU, 0) +#define SA_DEV_IPU PCI_DEV(0, SA_DEV_SLOT_IPU, 0) + #define SA_DEV_SLOT_TBT 0x07 #define SA_DEVFN_TBT0 PCI_DEVFN(SA_DEV_SLOT_TBT, 0) #define SA_DEVFN_TBT1 PCI_DEVFN(SA_DEV_SLOT_TBT, 1) @@ -40,9 +44,15 @@ #define SA_DEV_TBT2 PCI_DEV(0, SA_DEV_SLOT_TBT, 2) #define SA_DEV_TBT3 PCI_DEV(0, SA_DEV_SLOT_TBT, 3) -#define SA_DEV_SLOT_IPU 0x05 -#define SA_DEVFN_IPU PCI_DEVFN(SA_DEV_SLOT_IPU, 0) -#define SA_DEV_IPU PCI_DEV(0, SA_DEV_SLOT_IPU, 0) +#define SA_DEV_SLOT_TCSS 0x0d +#define SA_DEVFN_TCSS_XHCI PCI_DEVFN(SA_DEV_SLOT_TCSS, 0) +#define SA_DEVFN_TCSS_XDCI PCI_DEVFN(SA_DEV_SLOT_TCSS, 1) +#define SA_DEVFN_TCSS_DMA0 PCI_DEVFN(SA_DEV_SLOT_TCSS, 2) +#define SA_DEVFN_TCSS_DMA1 PCI_DEVFN(SA_DEV_SLOT_TCSS, 3) +#define SA_DEV_TCSS_XHCI PCI_DEV(0, SA_DEV_SLOT_TCSS, 0) +#define SA_DEV_TCSS_XDCI PCI_DEV(0, SA_DEV_SLOT_TCSS, 1) +#define SA_DEV_TCSS_DMA0 PCI_DEV(0, SA_DEV_SLOT_TCSS, 2) +#define SA_DEV_TCSS_DMA1 PCI_DEV(0, SA_DEV_SLOT_TCSS, 3) /* PCH Devices */ #define PCH_DEV_SLOT_SIO0 0x10 diff --git a/src/soc/intel/tigerlake/romstage/fsp_params.c b/src/soc/intel/tigerlake/romstage/fsp_params.c index a444623fa5..ede5059a5e 100644 --- a/src/soc/intel/tigerlake/romstage/fsp_params.c +++ b/src/soc/intel/tigerlake/romstage/fsp_params.c @@ -111,10 +111,14 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, /* Image clock: disable all clocks for bypassing FSP pin mux */ memset(m_cfg->ImguClkOutEn, 0, sizeof(m_cfg->ImguClkOutEn)); - /* Tcss */ + /* Tcss USB */ m_cfg->TcssXhciEn = config->TcssXhciEn; m_cfg->TcssXdciEn = config->TcssXdciEn; + /* TCSS DMA */ + m_cfg->TcssDma0En = config->TcssDma0En; + m_cfg->TcssDma1En = config->TcssDma1En; + /* USB4/TBT */ dev = pcidev_path_on_root(SA_DEVFN_TBT0); if (dev) |