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| author | Angel Pons <th3fanbus@gmail.com> | 2021-01-10 18:02:27 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-01-12 13:37:10 +0000 |
| commit | 83bdb4511632daeb67e53e8ed4b03e2165d4188e (patch) | |
| tree | ded45e63da8baba32948499bc2113f32f6e6b228 /src | |
| parent | 6279cabb5b0dc4a67525d61b1292bec40dee5360 (diff) | |
| download | coreboot-83bdb4511632daeb67e53e8ed4b03e2165d4188e.tar.xz | |
soc/intel/denverton_ns: Drop redundant `DEFAULT_ACPI_BASE`
It is only used in one place, and there's two other equivalent macros.
Change-Id: I7c8241e28f688abd2df8180559dd02ee441c7023
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49282
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/intel/denverton_ns/include/soc/iomap.h | 1 | ||||
| -rw-r--r-- | src/soc/intel/denverton_ns/pmc.c | 2 |
2 files changed, 1 insertions, 2 deletions
diff --git a/src/soc/intel/denverton_ns/include/soc/iomap.h b/src/soc/intel/denverton_ns/include/soc/iomap.h index fb5aafdfc8..c252ca11b6 100644 --- a/src/soc/intel/denverton_ns/include/soc/iomap.h +++ b/src/soc/intel/denverton_ns/include/soc/iomap.h @@ -12,7 +12,6 @@ /* Southbridge internal device IO BARs (Set to match FSP settings) */ #define DEFAULT_PMBASE 0x1800 -#define DEFAULT_ACPI_BASE DEFAULT_PMBASE #define ACPI_BASE_ADDRESS DEFAULT_PMBASE #define DEFAULT_TCO_BASE 0x400 diff --git a/src/soc/intel/denverton_ns/pmc.c b/src/soc/intel/denverton_ns/pmc.c index 8755825db2..258e6a4f83 100644 --- a/src/soc/intel/denverton_ns/pmc.c +++ b/src/soc/intel/denverton_ns/pmc.c @@ -16,7 +16,7 @@ /* While we read BAR dynamically in case it changed, let's * initialize it with a same value */ -static u16 acpi_base = DEFAULT_ACPI_BASE; +static u16 acpi_base = ACPI_BASE_ADDRESS; static u32 pwrm_base = DEFAULT_PWRM_BASE; static void pch_power_options(struct device *dev) { /* TODO */ } |