cpu/intel/haswell: Switch to POSTCAR_STAGE

Tested on Google Peppy (Acer C720).

Change-Id: I1802547d7a5b3875689cc4e126e7c189a75defa9
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/26793
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

6 files changed, 30 insertions, 396 deletions

diff --git a/src/cpu/intel/haswell/Makefile.inc b/src/cpu/intel/haswell/Makefile.inc
index dc7170b742..a0c892a561 100644
--- a/src/cpu/intel/haswell/Makefile.inc
+++ b/src/cpu/intel/haswell/Makefile.inc
@@ -9,17 +9,14 @@ ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smmrelocate.c
 ramstage-y += monotonic_timer.c
 
 romstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c
+postcar-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c
 
 smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c
 smm-$(CONFIG_HAVE_SMI_HANDLER) += tsc_freq.c
 smm-y += monotonic_timer.c
 
-ifneq ($(CONFIG_POSTCAR_STAGE),y)
-cpu_incs-y += $(src)/cpu/intel/haswell/cache_as_ram.inc
-else
 cpu_incs-y += $(src)/cpu/intel/car/non-evict/cache_as_ram.S
 postcar-y += ../car/non-evict/exit_car.S
-endif
 
 subdirs-y += ../../x86/tsc
 subdirs-y += ../../x86/mtrr
diff --git a/src/cpu/intel/haswell/cache_as_ram.inc b/src/cpu/intel/haswell/cache_as_ram.inc
deleted file mode 100644
index 388c2ea23c..0000000000
--- a/src/cpu/intel/haswell/cache_as_ram.inc
+++ /dev/null
@@ -1,297 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2000,2007 Ronald G. Minnich <rminnich@gmail.com>
- * Copyright (C) 2007-2008 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <cpu/x86/mtrr.h>
-#include <cpu/x86/cache.h>
-#include <cpu/x86/post_code.h>
-
-/* The full cache-as-ram size includes the cache-as-ram portion from coreboot
- * and the space used by the reference code. These 2 values combined should
- * be a power of 2 because the MTRR setup assumes that. */
-#define CACHE_AS_RAM_SIZE \
-	(CONFIG_DCACHE_RAM_SIZE + CONFIG_DCACHE_RAM_MRC_VAR_SIZE)
-#define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE
-
-/* Cache 4GB - MRC_SIZE_KB for MRC */
-#define CACHE_MRC_BYTES   ((CONFIG_CACHE_MRC_SIZE_KB << 10) - 1)
-#define CACHE_MRC_BASE    (0xFFFFFFFF - CACHE_MRC_BYTES)
-#define CACHE_MRC_MASK    (~CACHE_MRC_BYTES)
-
-#define CPU_PHYSMASK_HI  (1 << (CONFIG_CPU_ADDR_BITS - 32) - 1)
-
-#define NoEvictMod_MSR 0x2e0
-
-	/* Save the BIST result. */
-	movl	%eax, %ebp
-
-cache_as_ram:
-	post_code(0x20)
-
-	/* Send INIT IPI to all excluding ourself. */
-	movl	$0x000C4500, %eax
-	movl	$0xFEE00300, %esi
-	movl	%eax, (%esi)
-
-	/* All CPUs need to be in Wait for SIPI state */
-wait_for_sipi:
-	movl	(%esi), %eax
-	bt	$12, %eax
-	jc	wait_for_sipi
-
-	post_code(0x21)
-	/* Zero out all fixed range and variable range MTRRs. */
-	movl	$mtrr_table, %esi
-	movl	$((mtrr_table_end - mtrr_table) >> 1), %edi
-	xorl	%eax, %eax
-	xorl	%edx, %edx
-clear_mtrrs:
-	movw	(%esi), %bx
-	movzx	%bx, %ecx
-	wrmsr
-	add	$2, %esi
-	dec	%edi
-	jnz	clear_mtrrs
-
-	post_code(0x22)
-	/* Configure the default memory type to uncacheable. */
-	movl	$MTRR_DEF_TYPE_MSR, %ecx
-	rdmsr
-	andl	$(~0x00000cff), %eax
-	wrmsr
-
-	post_code(0x23)
-	/* Set Cache-as-RAM base address. */
-	movl	$(MTRR_PHYS_BASE(0)), %ecx
-	movl	$(CACHE_AS_RAM_BASE | MTRR_TYPE_WRBACK), %eax
-	xorl	%edx, %edx
-	wrmsr
-
-	post_code(0x24)
-	/* Set Cache-as-RAM mask. */
-	movl	$(MTRR_PHYS_MASK(0)), %ecx
-	movl	$(~(CACHE_AS_RAM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax
-	movl	$CPU_PHYSMASK_HI, %edx
-	wrmsr
-
-	post_code(0x25)
-
-	/* Enable MTRR. */
-	movl	$MTRR_DEF_TYPE_MSR, %ecx
-	rdmsr
-	orl	$MTRR_DEF_TYPE_EN, %eax
-	wrmsr
-
-	/* Enable cache (CR0.CD = 0, CR0.NW = 0). */
-	movl	%cr0, %eax
-	andl	$(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax
-	invd
-	movl	%eax, %cr0
-
-	/* enable the 'no eviction' mode */
-	movl    $NoEvictMod_MSR, %ecx
-	rdmsr
-	orl     $1, %eax
-	andl    $~2, %eax
-	wrmsr
-
-	/* Clear the cache memory region. This will also fill up the cache. */
-	movl	$CACHE_AS_RAM_BASE, %esi
-	movl	%esi, %edi
-	movl	$(CACHE_AS_RAM_SIZE >> 2), %ecx
-	// movl	$0x23322332, %eax
-	xorl	%eax, %eax
-	rep	stosl
-
-	/* enable the 'no eviction run' state */
-	movl    $NoEvictMod_MSR, %ecx
-	rdmsr
-	orl     $3, %eax
-	wrmsr
-
-	post_code(0x26)
-	/* Enable Cache-as-RAM mode by disabling cache. */
-	movl	%cr0, %eax
-	orl	$CR0_CacheDisable, %eax
-	movl	%eax, %cr0
-
-	/* Enable cache for our code in Flash because we do XIP here */
-	movl	$MTRR_PHYS_BASE(1), %ecx
-	xorl	%edx, %edx
-	/*
-	 * IMPORTANT: The following calculation _must_ be done at runtime. See
-	 * https://www.coreboot.org/pipermail/coreboot/2010-October/060855.html
-	 */
-	movl	$copy_and_run, %eax
-	andl	$(~(CONFIG_XIP_ROM_SIZE - 1)), %eax
-	orl	$MTRR_TYPE_WRPROT, %eax
-	wrmsr
-
-	movl	$MTRR_PHYS_MASK(1), %ecx
-	movl	$CPU_PHYSMASK_HI, %edx
-	movl	$(~(CONFIG_XIP_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax
-	wrmsr
-
-	post_code(0x27)
-	/* Enable caching for RAM init code to run faster */
-	movl	$MTRR_PHYS_BASE(2), %ecx
-	movl	$(CACHE_MRC_BASE | MTRR_TYPE_WRPROT), %eax
-	xorl	%edx, %edx
-	wrmsr
-	movl	$MTRR_PHYS_MASK(2), %ecx
-	movl	$(CACHE_MRC_MASK | MTRR_PHYS_MASK_VALID), %eax
-	movl	$CPU_PHYSMASK_HI, %edx
-	wrmsr
-
-	post_code(0x28)
-	/* Enable cache. */
-	movl	%cr0, %eax
-	andl	$(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax
-	movl	%eax, %cr0
-
-	/* Setup the stack. */
-	movl	$(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE), %eax
-	movl	%eax, %esp
-
-	/* Restore the BIST result. */
-	movl	%ebp, %eax
-	movl	%esp, %ebp
-	pushl	%eax
-
-before_romstage:
-	post_code(0x29)
-	/* Call romstage.c main function. */
-	call	romstage_main
-	/* Save return value from romstage_main. It contains the stack to use
-	 * after cache-as-ram is torn down. It also contains the information
-	 * for setting up MTRRs. */
-	movl	%eax, %esp
-
-	post_code(0x30)
-
-	/* Disable cache. */
-	movl	%cr0, %eax
-	orl	$CR0_CacheDisable, %eax
-	movl	%eax, %cr0
-
-	post_code(0x31)
-
-	/* Disable MTRR. */
-	movl	$MTRR_DEF_TYPE_MSR, %ecx
-	rdmsr
-	andl	$(~MTRR_DEF_TYPE_EN), %eax
-	wrmsr
-
-	post_code(0x32)
-
-	/* Disable the no eviction run state */
-	movl    $NoEvictMod_MSR, %ecx
-	rdmsr
-	andl    $~2, %eax
-	wrmsr
-
-	invd
-
-	/* Disable the no eviction mode */
-	rdmsr
-	andl    $~1, %eax
-	wrmsr
-
-	post_code(0x33)
-
-	/* Enable cache. */
-	movl	%cr0, %eax
-	andl	$~(CR0_CacheDisable | CR0_NoWriteThrough), %eax
-	movl	%eax, %cr0
-
-	post_code(0x36)
-
-	/* Disable cache. */
-	movl	%cr0, %eax
-	orl	$CR0_CacheDisable, %eax
-	movl	%eax, %cr0
-
-	post_code(0x38)
-
-	/* Get number of MTRRs. */
-	popl	%ebx
-	movl	$MTRR_PHYS_BASE(0), %ecx
-1:
-	testl	%ebx, %ebx
-	jz	1f
-
-	/* Low 32 bits of MTRR base. */
-	popl	%eax
-	/* Upper 32 bits of MTRR base. */
-	popl	%edx
-	/* Write MTRR base. */
-	wrmsr
-	inc	%ecx
-	/* Low 32 bits of MTRR mask. */
-	popl	%eax
-	/* Upper 32 bits of MTRR mask. */
-	popl	%edx
-	/* Write MTRR mask. */
-	wrmsr
-	inc	%ecx
-
-	dec	%ebx
-	jmp	1b
-1:
-	post_code(0x39)
-
-	/* And enable cache again after setting MTRRs. */
-	movl	%cr0, %eax
-	andl	$~(CR0_CacheDisable | CR0_NoWriteThrough), %eax
-	movl	%eax, %cr0
-
-	post_code(0x3a)
-
-	/* Enable MTRR. */
-	movl	$MTRR_DEF_TYPE_MSR, %ecx
-	rdmsr
-	orl	$MTRR_DEF_TYPE_EN, %eax
-	wrmsr
-
-	post_code(0x3b)
-
-	/* Invalidate the cache again. */
-	invd
-
-	post_code(0x3c)
-
-__main:
-	post_code(POST_PREPARE_RAMSTAGE)
-	cld			/* Clear direction flag. */
-	call	romstage_after_car
-
-.Lhlt:
-	post_code(POST_DEAD_CODE)
-	hlt
-	jmp	.Lhlt
-
-mtrr_table:
-	/* Fixed MTRRs */
-	.word 0x250, 0x258, 0x259
-	.word 0x268, 0x269, 0x26A
-	.word 0x26B, 0x26C, 0x26D
-	.word 0x26E, 0x26F
-	/* Variable MTRRs */
-	.word 0x200, 0x201, 0x202, 0x203
-	.word 0x204, 0x205, 0x206, 0x207
-	.word 0x208, 0x209, 0x20A, 0x20B
-	.word 0x20C, 0x20D, 0x20E, 0x20F
-	.word 0x210, 0x211, 0x212, 0x213
-mtrr_table_end:
diff --git a/src/cpu/intel/haswell/haswell.h b/src/cpu/intel/haswell/haswell.h
index 6612509e49..23efe6c443 100644
--- a/src/cpu/intel/haswell/haswell.h
+++ b/src/cpu/intel/haswell/haswell.h
@@ -181,9 +181,6 @@ void romstage_common(const struct romstage_params *params);
  *  ...
  */
 asmlinkage void *romstage_main(unsigned long bist);
-/* romstage_after_car() is the C function called after cache-as-ram has
- * been torn down. It is responsible for loading the ramstage. */
-asmlinkage void romstage_after_car(void);
 #endif
 
 #ifdef __SMM__
diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c
index 1c293d4647..ab9fd591be 100644
--- a/src/cpu/intel/haswell/romstage.c
+++ b/src/cpu/intel/haswell/romstage.c
@@ -50,100 +50,39 @@ static inline void reset_system(void)
 	halt();
 }
 
-/* The cache-as-ram assembly file calls romstage_main() after setting up
- * cache-as-ram.  romstage_main() will then call the mainboards's
- * mainboard_romstage_entry() function. That function then calls
- * romstage_common() below. The reason for the back and forth is to provide
- * common entry point from cache-as-ram while still allowing for code sharing.
- * Because we can't use global variables the stack is used for allocations --
- * thus the need to call back and forth. */
+#define ROMSTAGE_RAM_STACK_SIZE 0x5000
 
-
-static inline u32 *stack_push(u32 *stack, u32 value)
-{
-	stack = &stack[-1];
-	*stack = value;
-	return stack;
-}
-
-/* setup_romstage_stack_after_car() determines the stack to use after
- * cache-as-ram is torn down as well as the MTRR settings to use. */
-static void *setup_romstage_stack_after_car(void)
+/* platform_enter_postcar() determines the stack to use after
+ * cache-as-ram is torn down as well as the MTRR settings to use,
+ * and continues execution in postcar stage. */
+static void platform_enter_postcar(void)
 {
-	int num_mtrrs;
-	u32 *slot;
-	u32 mtrr_mask_upper;
-	u32 top_of_ram;
-
-	/* Top of stack needs to be aligned to a 4-byte boundary. */
-	slot = (void *)romstage_ram_stack_top();
-	num_mtrrs = 0;
-
-	/* The upper bits of the MTRR mask need to set according to the number
-	 * of physical address bits. */
-	mtrr_mask_upper = (1 << (cpu_phys_address_size() - 32)) - 1;
-
-	/* The order for each MTRR is value then base with upper 32-bits of
-	 * each value coming before the lower 32-bits. The reasoning for
-	 * this ordering is to create a stack layout like the following:
-	 *   +0: Number of MTRRs
-	 *   +4: MTRR base 0 31:0
-	 *   +8: MTRR base 0 63:32
-	 *  +12: MTRR mask 0 31:0
-	 *  +16: MTRR mask 0 63:32
-	 *  +20: MTRR base 1 31:0
-	 *  +24: MTRR base 1 63:32
-	 *  +28: MTRR mask 1 31:0
-	 *  +32: MTRR mask 1 63:32
-	 */
+	struct postcar_frame pcf;
+	uintptr_t top_of_ram;
 
+	if (postcar_frame_init(&pcf, ROMSTAGE_RAM_STACK_SIZE))
+		die("Unable to initialize postcar frame.\n");
 	/* Cache the ROM as WP just below 4GiB. */
-	slot = stack_push(slot, mtrr_mask_upper); /* upper mask */
-	slot = stack_push(slot, ~(CACHE_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID);
-	slot = stack_push(slot, 0); /* upper base */
-	slot = stack_push(slot, ~(CACHE_ROM_SIZE - 1) | MTRR_TYPE_WRPROT);
-	num_mtrrs++;
+	postcar_frame_add_mtrr(&pcf, CACHE_ROM_BASE, CACHE_ROM_SIZE,
+		MTRR_TYPE_WRPROT);
 
 	/* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */
-	slot = stack_push(slot, mtrr_mask_upper); /* upper mask */
-	slot = stack_push(slot, ~(CACHE_TMP_RAMTOP - 1) | MTRR_PHYS_MASK_VALID);
-	slot = stack_push(slot, 0); /* upper base */
-	slot = stack_push(slot, 0 | MTRR_TYPE_WRBACK);
-	num_mtrrs++;
-
-	top_of_ram = (uint32_t)cbmem_top();
-	/* Cache 8MiB below the top of RAM. On haswell systems the top of
-	 * RAM under 4GiB is the start of the TSEG region. It is required to
-	 * be 8MiB aligned. Set this area as cacheable so it can be used later
-	 * for ramstage before setting up the entire RAM as cacheable. */
-	slot = stack_push(slot, mtrr_mask_upper); /* upper mask */
-	slot = stack_push(slot, ~((8 << 20) - 1) | MTRR_PHYS_MASK_VALID);
-	slot = stack_push(slot, 0); /* upper base */
-	slot = stack_push(slot, (top_of_ram - (8 << 20)) | MTRR_TYPE_WRBACK);
-	num_mtrrs++;
-
-	/* Cache 8MiB at the top of RAM. Top of RAM on haswell systems
-	 * is where the TSEG region resides. However, it is not restricted
-	 * to SMM mode until SMM has been relocated. By setting the region
-	 * to cacheable it provides faster access when relocating the SMM
-	 * handler as well as using the TSEG region for other purposes. */
-	slot = stack_push(slot, mtrr_mask_upper); /* upper mask */
-	slot = stack_push(slot, ~((8 << 20) - 1) | MTRR_PHYS_MASK_VALID);
-	slot = stack_push(slot, 0); /* upper base */
-	slot = stack_push(slot, top_of_ram | MTRR_TYPE_WRBACK);
-	num_mtrrs++;
-
-	/* Save the number of MTRRs to setup. Return the stack location
-	 * pointing to the number of MTRRs. */
-	slot = stack_push(slot, num_mtrrs);
-
-	return slot;
+	postcar_frame_add_mtrr(&pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK);
+
+	/* Cache at least 8 MiB below the top of ram, and at most 8 MiB
+	 * above top of the ram. This satisfies MTRR alignment requirement
+	 * with different TSEG size configurations.
+	 */
+	top_of_ram = ALIGN_DOWN((uintptr_t)cbmem_top(), 8*MiB);
+	postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 16*MiB,
+			MTRR_TYPE_WRBACK);
+
+	run_postcar_phase(&pcf);
 }
 
 asmlinkage void *romstage_main(unsigned long bist)
 {
 	int i;
-	void *romstage_stack_after_car;
 	const int num_guards = 4;
 	const u32 stack_guard = 0xdeadbeef;
 	u32 *stack_base = (void *)(CONFIG_DCACHE_RAM_BASE +
@@ -163,10 +102,10 @@ asmlinkage void *romstage_main(unsigned long bist)
 		printk(BIOS_DEBUG, "Smashed stack detected in romstage!\n");
 	}
 
-	/* Get the stack to use after cache-as-ram is torn down. */
-	romstage_stack_after_car = setup_romstage_stack_after_car();
+	platform_enter_postcar();
 
-	return romstage_stack_after_car;
+	/* We do not return here */
+	return NULL;
 }
 
 void romstage_common(const struct romstage_params *params)
@@ -248,9 +187,3 @@ void romstage_common(const struct romstage_params *params)
 	if (IS_ENABLED(CONFIG_TPM1) || IS_ENABLED(CONFIG_TPM2))
 		tpm_setup(wake_from_s3);
 }
-
-asmlinkage void romstage_after_car(void)
-{
-	/* Load the ramstage. */
-	run_ramstage();
-}
diff --git a/src/northbridge/intel/haswell/Kconfig b/src/northbridge/intel/haswell/Kconfig
index 5c8caea92d..5e6956edf0 100644
--- a/src/northbridge/intel/haswell/Kconfig
+++ b/src/northbridge/intel/haswell/Kconfig
@@ -21,6 +21,8 @@ config NORTHBRIDGE_INTEL_HASWELL
 	select INTEL_GMA_ACPI
 	select RELOCATABLE_RAMSTAGE
 	select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM
+	select POSTCAR_STAGE
+	select POSTCAR_CONSOLE
 
 if NORTHBRIDGE_INTEL_HASWELL
 
diff --git a/src/northbridge/intel/haswell/Makefile.inc b/src/northbridge/intel/haswell/Makefile.inc
index c6d6b2eee8..055c2a8a0d 100644
--- a/src/northbridge/intel/haswell/Makefile.inc
+++ b/src/northbridge/intel/haswell/Makefile.inc
@@ -36,4 +36,6 @@ mrc.bin-file := $(call strip_quotes,$(CONFIG_MRC_FILE))
 mrc.bin-position := 0xfffa0000
 mrc.bin-type := mrc
 
+postcar-y += ram_calc.c
+
 endif