diff options
| author | Subrata Banik <subrata.banik@intel.com> | 2020-12-06 22:54:10 +0530 |
|---|---|---|
| committer | Subrata Banik <subrata.banik@intel.com> | 2020-12-08 06:37:06 +0000 |
| commit | 89b296c3fe844347afa5dfa2b7c4089d0bda82da (patch) | |
| tree | 9d49aab45c242cdf29e518ae79a0a205c1244640 /src | |
| parent | cdd9db340b73cae36775133244e3f379d6402c69 (diff) | |
| download | coreboot-89b296c3fe844347afa5dfa2b7c4089d0bda82da.tar.xz | |
soc/intel/common/block/cpu/car: Fix two whitespace issues
This patch removes 1 unnecessary whitespace and add 1 whitespace into IA
common car code block.
Change-Id: I3690b5f219f5326cfca7956f21132062aa89648e
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48381
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/intel/common/block/cpu/Kconfig | 2 | ||||
| -rw-r--r-- | src/soc/intel/common/block/cpu/car/cache_as_ram.S | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/src/soc/intel/common/block/cpu/Kconfig b/src/soc/intel/common/block/cpu/Kconfig index 9023b58d54..1ec7af5cd4 100644 --- a/src/soc/intel/common/block/cpu/Kconfig +++ b/src/soc/intel/common/block/cpu/Kconfig @@ -64,7 +64,7 @@ config USE_CAR_NEM_ENHANCED_V2 select COS_MAPPED_TO_MSB help This config supports INTEL_CAR_NEM_ENHANCED mode on - TGL platform. + TGL platform. config COS_MAPPED_TO_MSB bool diff --git a/src/soc/intel/common/block/cpu/car/cache_as_ram.S b/src/soc/intel/common/block/cpu/car/cache_as_ram.S index 167342f12e..97bffb0062 100644 --- a/src/soc/intel/common/block/cpu/car/cache_as_ram.S +++ b/src/soc/intel/common/block/cpu/car/cache_as_ram.S @@ -413,7 +413,7 @@ find_llc_subleaf: set_eviction_mask: mov %ebx, %ecx /* back up the number of ways */ - mov %eax, %ebx /* back up the non-eviction mask*/ + mov %eax, %ebx /* back up the non-eviction mask */ /* * Set MSR 0xC91 IA32_L3_MASK_1 or MSR 0x1891 IA32_CR_SF_QOS_MASK_1 * This MSR contain one bit per each way of LLC |