diff options
| author | Arthur Heymans <arthur@aheymans.xyz> | 2016-10-16 10:58:01 +0200 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-10-19 17:04:37 +0200 |
| commit | 8b6df62fc21dc167979c03aa88cfe9cf03a115a8 (patch) | |
| tree | 2e9d742f3f908ccedf19b778ad8fad31f884255f /src | |
| parent | e1897616038f78015633134fc38e351c33a46975 (diff) | |
| download | coreboot-8b6df62fc21dc167979c03aa88cfe9cf03a115a8.tar.xz | |
nb/i945/raminit: Add fix for clock crossing for 800MHz FSB CPU
The cross clocking of 800MHz FSB CPU with 667MHz RAM was incorrect.
The result is that 800MHz FSB CPUs now properly work with 667MHz RAM.
Value taken from vendor bios on ga-945gcm-s2l and suggested by Haouas
Elyes.
Change-Id: I56c12af50c75a735af0150a4e7bce4faacc93648
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/17038
Tested-by: build bot (Jenkins)
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src')
| -rw-r--r-- | src/northbridge/intel/i945/raminit.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index 1ec2dc5ef4..dbd5d42089 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -2261,7 +2261,7 @@ static void sdram_program_clock_crossing(void) 0x02010804, 0x00000000, /* DDR400 FSB800 */ 0x00010402, 0x00000000, /* DDR533 FSB800 */ - 0x04020180, 0x00000008, /* DDR667 FSB800 */ + 0x04020130, 0x00000008, /* DDR667 FSB800 */ 0x00020904, 0x00000000, /* DDR400 FSB1066 */ 0x02010804, 0x00000000, /* DDR533 FSB1066 */ |