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authorAngel Pons <th3fanbus@gmail.com>2020-07-22 16:04:15 +0200
committerPatrick Georgi <pgeorgi@google.com>2020-08-03 05:28:42 +0000
commit9333b742295a1e8eb630b2e73fcac43318e10b6a (patch)
tree1b433f59fcc2d71d2163ced452695b5c9b9fc73f /src
parent8bf160a9a620762d2ff36671c9cb3c693418d110 (diff)
downloadcoreboot-9333b742295a1e8eb630b2e73fcac43318e10b6a.tar.xz
nb/intel/ironlake: Rename memory map variables
Uppercase variable names can be confused with register definitions. Use lowercase names instead, conforming to the coding style guidelines. Tested with BUILD_TIMELESS=1, Packard Bell MS2290 remains identical. Change-Id: I61a28bf964ea8c2c662539825ae9f2c88348bdba Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43730 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src')
-rw-r--r--src/northbridge/intel/ironlake/northbridge.c12
-rw-r--r--src/northbridge/intel/ironlake/raminit.c40
2 files changed, 26 insertions, 26 deletions
diff --git a/src/northbridge/intel/ironlake/northbridge.c b/src/northbridge/intel/ironlake/northbridge.c
index c1a2840bda..4cd098ce92 100644
--- a/src/northbridge/intel/ironlake/northbridge.c
+++ b/src/northbridge/intel/ironlake/northbridge.c
@@ -94,7 +94,7 @@ static struct device_operations pci_domain_ops = {
static void mc_read_resources(struct device *dev)
{
uint32_t tseg_base;
- uint64_t TOUUD;
+ uint64_t touud;
uint16_t reg16;
pci_dev_read_resources(dev);
@@ -102,11 +102,11 @@ static void mc_read_resources(struct device *dev)
mmconf_resource(dev, 0x50);
tseg_base = pci_read_config32(pcidev_on_root(0, 0), TSEG);
- TOUUD = pci_read_config16(pcidev_on_root(0, 0),
+ touud = pci_read_config16(pcidev_on_root(0, 0),
D0F0_TOUUD);
printk(BIOS_DEBUG, "ram_before_4g_top: 0x%x\n", tseg_base);
- printk(BIOS_DEBUG, "TOUUD: 0x%x\n", (unsigned int)TOUUD);
+ printk(BIOS_DEBUG, "TOUUD: 0x%x\n", (unsigned int)touud);
/* Report the memory regions */
ram_resource(dev, 3, 0, 640);
@@ -134,11 +134,11 @@ static void mc_read_resources(struct device *dev)
mmio_resource(dev, 6, gtt_base >> 10, uma_size_gtt << 10);
mmio_resource(dev, 7, igd_base >> 10, uma_size_igd << 10);
- if (TOUUD > 4096)
- ram_resource(dev, 8, (4096 << 10), ((TOUUD - 4096) << 10));
+ if (touud > 4096)
+ ram_resource(dev, 8, (4096 << 10), ((touud - 4096) << 10));
/* This memory is not DMA-capable. */
- if (TOUUD >= 8192 - 64)
+ if (touud >= 8192 - 64)
bad_ram_resource(dev, 9, 0x1fc000000ULL >> 10, 0x004000000 >> 10);
add_fixed_resources(dev, 10);
diff --git a/src/northbridge/intel/ironlake/raminit.c b/src/northbridge/intel/ironlake/raminit.c
index 494db19f73..8b28e51394 100644
--- a/src/northbridge/intel/ironlake/raminit.c
+++ b/src/northbridge/intel/ironlake/raminit.c
@@ -1364,9 +1364,9 @@ static unsigned int get_mmio_size(void)
static void program_total_memory_map(struct raminfo *info)
{
- unsigned int TOM, TOLUD, TOUUD;
+ unsigned int tom, tolud, touud;
unsigned int quickpath_reserved;
- unsigned int REMAPbase;
+ unsigned int remap_base;
unsigned int uma_base_igd;
unsigned int uma_base_gtt;
unsigned int mmio_size;
@@ -1396,20 +1396,20 @@ static void program_total_memory_map(struct raminfo *info)
mmio_size = get_mmio_size();
- TOM = info->total_memory_mb;
- if (TOM == 4096)
- TOM = 4032;
- TOUUD = ALIGN_DOWN(TOM - info->memory_reserved_for_heci_mb, 64);
- TOLUD = ALIGN_DOWN(MIN(4096 - mmio_size + ALIGN_UP(uma_size_igd + uma_size_gtt, 64)
- , TOUUD), 64);
+ tom = info->total_memory_mb;
+ if (tom == 4096)
+ tom = 4032;
+ touud = ALIGN_DOWN(tom - info->memory_reserved_for_heci_mb, 64);
+ tolud = ALIGN_DOWN(MIN(4096 - mmio_size + ALIGN_UP(uma_size_igd + uma_size_gtt, 64)
+ , touud), 64);
memory_remap = 0;
- if (TOUUD - TOLUD > 64) {
+ if (touud - tolud > 64) {
memory_remap = 1;
- REMAPbase = MAX(4096, TOUUD);
- TOUUD = TOUUD - TOLUD + 4096;
+ remap_base = MAX(4096, touud);
+ touud = touud - tolud + 4096;
}
- if (TOUUD > 4096)
- memory_map[2] = TOUUD | 1;
+ if (touud > 4096)
+ memory_map[2] = touud | 1;
quickpath_reserved = 0;
u32 t = pci_read_config32(PCI_DEV(QUICKPATH_BUS, 0, 1), 0x68);
@@ -1424,22 +1424,22 @@ static void program_total_memory_map(struct raminfo *info)
}
if (memory_remap)
- TOUUD -= quickpath_reserved;
+ touud -= quickpath_reserved;
- uma_base_igd = TOLUD - uma_size_igd;
+ uma_base_igd = tolud - uma_size_igd;
uma_base_gtt = uma_base_igd - uma_size_gtt;
tseg_base = ALIGN_DOWN(uma_base_gtt, 64) - (CONFIG_SMM_TSEG_SIZE >> 20);
if (!memory_remap)
tseg_base -= quickpath_reserved;
tseg_base = ALIGN_DOWN(tseg_base, 8);
- pci_write_config16(NORTHBRIDGE, D0F0_TOLUD, TOLUD << 4);
- pci_write_config16(NORTHBRIDGE, D0F0_TOM, TOM >> 6);
+ pci_write_config16(NORTHBRIDGE, D0F0_TOLUD, tolud << 4);
+ pci_write_config16(NORTHBRIDGE, D0F0_TOM, tom >> 6);
if (memory_remap) {
- pci_write_config16(NORTHBRIDGE, D0F0_REMAPBASE, REMAPbase >> 6);
- pci_write_config16(NORTHBRIDGE, D0F0_REMAPLIMIT, (TOUUD - 64) >> 6);
+ pci_write_config16(NORTHBRIDGE, D0F0_REMAPBASE, remap_base >> 6);
+ pci_write_config16(NORTHBRIDGE, D0F0_REMAPLIMIT, (touud - 64) >> 6);
}
- pci_write_config16(NORTHBRIDGE, D0F0_TOUUD, TOUUD);
+ pci_write_config16(NORTHBRIDGE, D0F0_TOUUD, touud);
if (info->uma_enabled) {
pci_write_config32(NORTHBRIDGE, D0F0_IGD_BASE, uma_base_igd << 20);