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authorAngel Pons <th3fanbus@gmail.com>2021-05-17 14:30:50 +0200
committerPatrick Georgi <pgeorgi@google.com>2021-05-20 17:47:40 +0000
commit945fe766a1c4cc939fbc5da03259d4d8c413bfa5 (patch)
treea2a33460ce90a6fa32ad3bdffc84ccb12ffe21a0 /src
parent348639c4603852f70c161aa58b986e1a7e37962e (diff)
downloadcoreboot-945fe766a1c4cc939fbc5da03259d4d8c413bfa5.tar.xz
mb/asus/p8h61-m_lx3_r2_0: Extract overridetree
Tested with BUILD_TIMELESS=1, coreboot.rom for the Asus P8H61-M LX3 R2.0 remains identical when not adding the .config file in it. Change-Id: I989f69d000a38a7b1f4e0832341aa347cc0bfe98 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54387 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
-rw-r--r--src/mainboard/asus/h61-series/Kconfig12
-rw-r--r--src/mainboard/asus/h61-series/devicetree.cb50
-rw-r--r--src/mainboard/asus/h61-series/variants/p8h61-m_lx3_r2_0/overridetree.cb (renamed from src/mainboard/asus/h61-series/variants/p8h61-m_lx3_r2_0/devicetree.cb)31
3 files changed, 62 insertions, 31 deletions
diff --git a/src/mainboard/asus/h61-series/Kconfig b/src/mainboard/asus/h61-series/Kconfig
index e776a54813..21975cf273 100644
--- a/src/mainboard/asus/h61-series/Kconfig
+++ b/src/mainboard/asus/h61-series/Kconfig
@@ -32,10 +32,22 @@ config MAINBOARD_PART_NUMBER
default "P8H61-M LX3 R2.0" if BOARD_ASUS_P8H61_M_LX3_R2_0
default "P8H61-M PRO" if BOARD_ASUS_P8H61_M_PRO
+# TODO: remove once all boards use overridetrees
+if BOARD_ASUS_P8H61_M_LX3_R2_0
+
+config OVERRIDE_DEVICETREE
+ string
+ default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb"
+
+endif
+if !BOARD_ASUS_P8H61_M_LX3_R2_0
+
config DEVICETREE
string
default "variants/\$(CONFIG_VARIANT_DIR)/devicetree.cb"
+endif
+
config CMOS_DEFAULT_FILE
default "src/mainboard/\$(MAINBOARDDIR)/variants/\$(CONFIG_VARIANT_DIR)/cmos.default"
diff --git a/src/mainboard/asus/h61-series/devicetree.cb b/src/mainboard/asus/h61-series/devicetree.cb
new file mode 100644
index 0000000000..07c0a866c3
--- /dev/null
+++ b/src/mainboard/asus/h61-series/devicetree.cb
@@ -0,0 +1,50 @@
+## SPDX-License-Identifier: GPL-2.0-or-later
+
+chip northbridge/intel/sandybridge
+ device cpu_cluster 0 on
+ chip cpu/intel/model_206ax
+ register "acpi_c1" = "1"
+ register "acpi_c2" = "3"
+ register "acpi_c3" = "5"
+ device lapic 0 on end
+ device lapic 0xacac off end
+ end
+ end
+ device domain 0 on
+ device pci 00.0 on end # Host bridge
+ device pci 01.0 on end # PEG
+ device pci 02.0 on end # iGPU
+
+ chip southbridge/intel/bd82x6x
+ register "c2_latency" = "0x0065"
+ register "sata_port_map" = "0x33"
+ register "spi_lvscc" = "0x2005"
+ register "spi_uvscc" = "0x2005"
+
+ device pci 16.0 on end # MEI #1
+ device pci 16.1 off end # MEI #2
+ device pci 16.2 off end # ME IDE-R
+ device pci 16.3 off end # ME KT
+ device pci 19.0 off end # Intel GbE
+ device pci 1a.0 on end # EHCI #2
+ device pci 1b.0 on end # HD Audio
+
+ device pci 1c.0 off end # RP #1
+ device pci 1c.1 off end # RP #2
+ device pci 1c.2 off end # RP #3
+ device pci 1c.3 off end # RP #4
+ device pci 1c.4 off end # RP #5
+ device pci 1c.5 off end # RP #6
+ device pci 1c.6 off end # RP #7
+ device pci 1c.7 off end # RP #8
+
+ device pci 1d.0 on end # EHCI #1
+ device pci 1e.0 off end # PCI bridge
+ device pci 1f.0 on end # LPC bridge
+ device pci 1f.2 on end # SATA (AHCI)
+ device pci 1f.3 on end # SMBus
+ device pci 1f.5 off end # SATA (Legacy)
+ device pci 1f.6 off end # Thermal
+ end
+ end
+end
diff --git a/src/mainboard/asus/h61-series/variants/p8h61-m_lx3_r2_0/devicetree.cb b/src/mainboard/asus/h61-series/variants/p8h61-m_lx3_r2_0/overridetree.cb
index 1ae77ad2b0..5d9635c15a 100644
--- a/src/mainboard/asus/h61-series/variants/p8h61-m_lx3_r2_0/devicetree.cb
+++ b/src/mainboard/asus/h61-series/variants/p8h61-m_lx3_r2_0/overridetree.cb
@@ -1,35 +1,10 @@
## SPDX-License-Identifier: GPL-2.0-or-later
chip northbridge/intel/sandybridge
- device cpu_cluster 0 on
- chip cpu/intel/model_206ax
- register "acpi_c1" = "1"
- register "acpi_c2" = "3"
- register "acpi_c3" = "5"
- device lapic 0 on end
- device lapic 0xacac off end
- end
- end
device domain 0 on
subsystemid 0x1043 0x844d inherit
- device pci 00.0 on end # Host bridge
- device pci 01.0 on end # PEG
- device pci 02.0 on end # iGPU
-
chip southbridge/intel/bd82x6x
- register "c2_latency" = "0x0065"
register "gen1_dec" = "0x000c0291"
- register "sata_port_map" = "0x33"
- register "spi_lvscc" = "0x2005"
- register "spi_uvscc" = "0x2005"
-
- device pci 16.0 on end # MEI #1
- device pci 16.1 off end # MEI #2
- device pci 16.2 off end # ME IDE-R
- device pci 16.3 off end # ME KT
- device pci 19.0 off end # Intel GbE
- device pci 1a.0 on end # USB2 EHCI #2
- device pci 1b.0 on end # HD Audio
device pci 1c.0 on end # RP #1
device pci 1c.1 off end # RP #2
@@ -40,8 +15,6 @@ chip northbridge/intel/sandybridge
device pci 1c.6 off end # RP #7
device pci 1c.7 off end # RP #8
- device pci 1d.0 on end # USB2 EHCI #1
- device pci 1e.0 off end # PCI bridge
device pci 1f.0 on # LPC bridge
chip superio/nuvoton/nct6779d
device pnp 2e.1 off end # Parallel
@@ -78,10 +51,6 @@ chip northbridge/intel/sandybridge
device pnp 2e.16 off end # Deep Sleep
end
end
- device pci 1f.2 on end # SATA (AHCI)
- device pci 1f.3 on end # SMBus
- device pci 1f.5 off end # SATA (Legacy)
- device pci 1f.6 off end # Thermal
end
end
end