Unify DIMM SPD addressing. For Geode, change the

addressing scheme to match the rest of the tree
(0x50 instead of 0xa0).

abuild tested.

Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6099 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

47 files changed, 54 insertions, 191 deletions

diff --git a/src/include/spd.h b/src/include/spd.h
index 53031c12e4..8aaad6b25d 100644
--- a/src/include/spd.h
+++ b/src/include/spd.h
@@ -156,5 +156,15 @@
 #define MODULE_BUFFERED                  1
 #define MODULE_REGISTERED                2
 
+/* DIMM SPD addresses */
+#define DIMM0                            0x50
+#define DIMM1                            0x51
+#define DIMM2                            0x52
+#define DIMM3                            0x53
+#define DIMM4                            0x54
+#define DIMM5                            0x55
+#define DIMM6                            0x56
+#define DIMM7                            0x57
+
 #endif /* _SPD_H_ */
 
diff --git a/src/mainboard/amd/db800/romstage.c b/src/mainboard/amd/db800/romstage.c
index 0f2ec7fce0..8977b27bd4 100644
--- a/src/mainboard/amd/db800/romstage.c
+++ b/src/mainboard/amd/db800/romstage.c
@@ -30,6 +30,7 @@
 #include <cpu/amd/lxdef.h>
 #include <cpu/amd/geode_post_code.h>
 #include "southbridge/amd/cs5536/cs5536.h"
+#include <spd.h>
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
 
@@ -45,8 +46,6 @@ static inline int spd_read_byte(unsigned int device, unsigned int address)
 #define ManualConf 0		/* Do automatic strapped PLL config */
 #define PLLMSRhi 0x000005DD	/* Manual settings for the PLL */
 #define PLLMSRlo 0x00DE60EE
-#define DIMM0 0xA0
-#define DIMM1 0xA2
 
 #include "northbridge/amd/lx/raminit.h"
 #include "northbridge/amd/lx/pll_reset.c"
diff --git a/src/mainboard/amd/dbm690t/romstage.c b/src/mainboard/amd/dbm690t/romstage.c
index 8c8978785c..94d4fc457a 100644
--- a/src/mainboard/amd/dbm690t/romstage.c
+++ b/src/mainboard/amd/dbm690t/romstage.c
@@ -20,9 +20,6 @@
 #define RC0 (6<<8)
 #define RC1 (7<<8)
 
-#define DIMM0 0x50
-#define DIMM1 0x51
-
 #define SMBUS_HUB 0x71
 
 #include <stdint.h>
@@ -43,6 +40,7 @@
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "superio/ite/it8712f/it8712f_early_serial.c"
+#include <spd.h>
 
 #include <usbdebug.h>
 
diff --git a/src/mainboard/amd/mahogany/romstage.c b/src/mainboard/amd/mahogany/romstage.c
index 39e6675496..d4d70abcea 100644
--- a/src/mainboard/amd/mahogany/romstage.c
+++ b/src/mainboard/amd/mahogany/romstage.c
@@ -20,9 +20,6 @@
 #define RC0 (6<<8)
 #define RC1 (7<<8)
 
-#define DIMM0 0x50
-#define DIMM1 0x51
-
 #define SMBUS_HUB 0x71
 
 #include <stdint.h>
@@ -34,6 +31,7 @@
 #include <cpu/x86/lapic.h>
 #include <pc80/mc146818rtc.h>
 #include <console/console.h>
+#include <spd.h>
 
 #include <cpu/amd/model_fxx_rev.h>
 #include "northbridge/amd/amdk8/raminit.h"
diff --git a/src/mainboard/amd/mahogany_fam10/romstage.c b/src/mainboard/amd/mahogany_fam10/romstage.c
index 3e6466e72c..abb2a114f8 100644
--- a/src/mainboard/amd/mahogany_fam10/romstage.c
+++ b/src/mainboard/amd/mahogany_fam10/romstage.c
@@ -57,6 +57,7 @@ static int smbus_read_byte(u32 device, u32 address);
 #include "southbridge/amd/rs780/rs780_early_setup.c"
 #include "southbridge/amd/sb700/sb700_early_setup.c"
 #include "northbridge/amd/amdfam10/debug.c"
+#include <spd.h>
 
 static void activate_spd_rom(const struct mem_controller *ctrl)
 {
@@ -90,11 +91,6 @@ static int spd_read_byte(u32 device, u32 address)
 #define RC00  0
 #define RC01  1
 
-#define DIMM0 0x50
-#define DIMM1 0x51
-#define DIMM2 0x52
-#define DIMM3 0x53
-
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
 
diff --git a/src/mainboard/amd/norwich/romstage.c b/src/mainboard/amd/norwich/romstage.c
index e957d7ea94..1211610421 100644
--- a/src/mainboard/amd/norwich/romstage.c
+++ b/src/mainboard/amd/norwich/romstage.c
@@ -30,6 +30,7 @@
 #include <cpu/amd/lxdef.h>
 #include <cpu/amd/geode_post_code.h>
 #include "southbridge/amd/cs5536/cs5536.h"
+#include <spd.h>
 
 #include "southbridge/amd/cs5536/cs5536_early_smbus.c"
 #include "southbridge/amd/cs5536/cs5536_early_setup.c"
@@ -42,8 +43,6 @@ static inline int spd_read_byte(unsigned int device, unsigned int address)
 #define ManualConf 0		/* Do automatic strapped PLL config */
 #define PLLMSRhi 0x00001490	/* manual settings for the PLL */
 #define PLLMSRlo 0x02000030
-#define DIMM0 0xA0
-#define DIMM1 0xA2
 
 #include "northbridge/amd/lx/raminit.h"
 #include "northbridge/amd/lx/pll_reset.c"
diff --git a/src/mainboard/amd/pistachio/romstage.c b/src/mainboard/amd/pistachio/romstage.c
index 740b148f7e..f1f61c3d0c 100644
--- a/src/mainboard/amd/pistachio/romstage.c
+++ b/src/mainboard/amd/pistachio/romstage.c
@@ -17,9 +17,6 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-#define DIMM0 0x50
-#define DIMM1 0x51
-
 #include <stdint.h>
 #include <string.h>
 #include <device/pci_def.h>
@@ -39,6 +36,7 @@
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "superio/ite/it8712f/it8712f_early_serial.c"
 #include <usbdebug.h>
+#include <spd.h>
 
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"
diff --git a/src/mainboard/amd/rumba/romstage.c b/src/mainboard/amd/rumba/romstage.c
index f8cd775f02..e08d967471 100644
--- a/src/mainboard/amd/rumba/romstage.c
+++ b/src/mainboard/amd/rumba/romstage.c
@@ -9,15 +9,13 @@
 #include "cpu/x86/msr.h"
 #include <cpu/amd/gx2def.h>
 #include <cpu/amd/geode_post_code.h>
+#include <spd.h>
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
 
 #include "southbridge/amd/cs5536/cs5536_early_smbus.c"
 #include "southbridge/amd/cs5536/cs5536_early_setup.c"
 
-#define DIMM0 0xA0
-#define DIMM1 0xFF /* DIMM1 is not available/used on this board. */
-
 static inline int spd_read_byte(unsigned device, unsigned address)
 {
  	if (device != DIMM0)
diff --git a/src/mainboard/amd/serengeti_cheetah/romstage.c b/src/mainboard/amd/serengeti_cheetah/romstage.c
index 24a4bf44f8..40f6b7be1c 100644
--- a/src/mainboard/amd/serengeti_cheetah/romstage.c
+++ b/src/mainboard/amd/serengeti_cheetah/romstage.c
@@ -92,22 +92,13 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #include "resourcemap.c"
 
 #include "cpu/amd/dualcore/dualcore.c"
+#include <spd.h>
 
 #define RC0 ((1<<0)<<8)
 #define RC1 ((1<<1)<<8)
 #define RC2 ((1<<2)<<8)
 #define RC3 ((1<<3)<<8)
 
-#define DIMM0 0x50
-#define DIMM1 0x51
-#define DIMM2 0x52
-#define DIMM3 0x53
-#define DIMM4 0x54
-#define DIMM5 0x55
-#define DIMM6 0x56
-#define DIMM7 0x57
-
-
 #include "cpu/amd/car/post_cache_as_ram.c"
 
 #include "cpu/amd/model_fxx/init_cpus.c"
diff --git a/src/mainboard/amd/tilapia_fam10/romstage.c b/src/mainboard/amd/tilapia_fam10/romstage.c
index eef7c8c466..c73a07c357 100644
--- a/src/mainboard/amd/tilapia_fam10/romstage.c
+++ b/src/mainboard/amd/tilapia_fam10/romstage.c
@@ -84,17 +84,13 @@ static int spd_read_byte(u32 device, u32 address)
 
 #include "northbridge/amd/amdfam10/early_ht.c"
 #include "southbridge/amd/sb700/sb700_early_setup.c"
+#include <spd.h>
 
 //#include "spd_addr.h"
 
 #define RC00  0
 #define RC01  1
 
-#define DIMM0 0x50
-#define DIMM1 0x51
-#define DIMM2 0x52
-#define DIMM3 0x53
-
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
 
diff --git a/src/mainboard/artecgroup/dbe61/romstage.c b/src/mainboard/artecgroup/dbe61/romstage.c
index dc4e3ffe26..8303b15f49 100644
--- a/src/mainboard/artecgroup/dbe61/romstage.c
+++ b/src/mainboard/artecgroup/dbe61/romstage.c
@@ -32,13 +32,11 @@
 #include <cpu/amd/geode_post_code.h>
 #include "southbridge/amd/cs5536/cs5536.h"
 #include "spd_table.h"
+#include <spd.h>
 
 #include "southbridge/amd/cs5536/cs5536_early_smbus.c"
 #include "southbridge/amd/cs5536/cs5536_early_setup.c"
 
-#define DIMM0 0xA0
-#define DIMM1 0xA2
-
 static int spd_read_byte(unsigned device, unsigned address)
 {
 	int i;
diff --git a/src/mainboard/asrock/939a785gmh/romstage.c b/src/mainboard/asrock/939a785gmh/romstage.c
index da0f9ac92d..7fb3227661 100644
--- a/src/mainboard/asrock/939a785gmh/romstage.c
+++ b/src/mainboard/asrock/939a785gmh/romstage.c
@@ -21,9 +21,6 @@
 #define RC0 (6<<8)
 #define RC1 (7<<8)
 
-#define DIMM0 0x50
-#define DIMM1 0x51
-
 #define SMBUS_HUB 0x71
 
 #include <stdint.h>
@@ -40,6 +37,7 @@
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
+#include <spd.h>
 
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"
diff --git a/src/mainboard/asus/m4a785-m/romstage.c b/src/mainboard/asus/m4a785-m/romstage.c
index 46b16a3fc5..f6e242b8ea 100644
--- a/src/mainboard/asus/m4a785-m/romstage.c
+++ b/src/mainboard/asus/m4a785-m/romstage.c
@@ -84,17 +84,13 @@ static int spd_read_byte(u32 device, u32 address)
 
 #include "northbridge/amd/amdfam10/early_ht.c"
 #include "southbridge/amd/sb700/sb700_early_setup.c"
+#include <spd.h>
 
 //#include "spd_addr.h"
 
 #define RC00  0
 #define RC01  1
 
-#define DIMM0 0x50
-#define DIMM1 0x51
-#define DIMM2 0x52
-#define DIMM3 0x53
-
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
 
diff --git a/src/mainboard/broadcom/blast/romstage.c b/src/mainboard/broadcom/blast/romstage.c
index f55f265674..0a4bc19437 100644
--- a/src/mainboard/broadcom/blast/romstage.c
+++ b/src/mainboard/broadcom/blast/romstage.c
@@ -70,16 +70,11 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #include "resourcemap.c"
 
 #include "cpu/amd/dualcore/dualcore.c"
+#include <spd.h>
 
 #define RC0 (6<<8)
 #define RC1 (7<<8)
 
-#define DIMM0 0x50
-#define DIMM1 0x51
-#define DIMM2 0x52
-#define DIMM3 0x53
-
-
 #include "cpu/amd/car/post_cache_as_ram.c"
 
 #include "cpu/amd/model_fxx/init_cpus.c"
diff --git a/src/mainboard/digitallogic/msm800sev/romstage.c b/src/mainboard/digitallogic/msm800sev/romstage.c
index 3b2d8f1dbb..6cf6ec6f19 100644
--- a/src/mainboard/digitallogic/msm800sev/romstage.c
+++ b/src/mainboard/digitallogic/msm800sev/romstage.c
@@ -11,6 +11,7 @@
 #include <cpu/amd/lxdef.h>
 #include <cpu/amd/geode_post_code.h>
 #include "southbridge/amd/cs5536/cs5536.h"
+#include <spd.h>
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
 
@@ -26,8 +27,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #define ManualConf 0		/* Do automatic strapped PLL config */
 #define PLLMSRhi 0x00001490 /* manual settings for the PLL */
 #define PLLMSRlo 0x02000030
-#define DIMM0 0xA0
-#define DIMM1 0xA2
 #include "northbridge/amd/lx/raminit.h"
 #include "northbridge/amd/lx/pll_reset.c"
 #include "northbridge/amd/lx/raminit.c"
diff --git a/src/mainboard/gigabyte/ma785gmt/romstage.c b/src/mainboard/gigabyte/ma785gmt/romstage.c
index 7656d4f12b..3286e028f4 100644
--- a/src/mainboard/gigabyte/ma785gmt/romstage.c
+++ b/src/mainboard/gigabyte/ma785gmt/romstage.c
@@ -80,16 +80,12 @@ static int spd_read_byte(u32 device, u32 address)
 
 #include "northbridge/amd/amdfam10/early_ht.c"
 #include "southbridge/amd/sb700/sb700_early_setup.c"
+#include <spd.h>
 
 
 #define RC00  0
 #define RC01  1
 
-#define DIMM0 0x50
-#define DIMM1 0x51
-#define DIMM2 0x52
-#define DIMM3 0x53
-
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
 
diff --git a/src/mainboard/gigabyte/ma78gm/romstage.c b/src/mainboard/gigabyte/ma78gm/romstage.c
index 555b447a70..a61be0a9ab 100644
--- a/src/mainboard/gigabyte/ma78gm/romstage.c
+++ b/src/mainboard/gigabyte/ma78gm/romstage.c
@@ -84,16 +84,12 @@ static int spd_read_byte(u32 device, u32 address)
 
 #include "northbridge/amd/amdfam10/early_ht.c"
 #include "southbridge/amd/sb700/sb700_early_setup.c"
+#include <spd.h>
 
 
 #define RC00  0
 #define RC01  1
 
-#define DIMM0 0x50
-#define DIMM1 0x51
-#define DIMM2 0x52
-#define DIMM3 0x53
-
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
 
diff --git a/src/mainboard/hp/dl145_g1/romstage.c b/src/mainboard/hp/dl145_g1/romstage.c
index 2ba791871c..f5fdf35eb9 100644
--- a/src/mainboard/hp/dl145_g1/romstage.c
+++ b/src/mainboard/hp/dl145_g1/romstage.c
@@ -92,15 +92,11 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #include "lib/generic_sdram.c"
 
 #include "cpu/amd/dualcore/dualcore.c"
+#include <spd.h>
 
 #define RC0 ((1<<1)<<8) // Not sure about these values
 #define RC1 ((1<<2)<<8) // Not sure about these values
 
-#define DIMM0 0x50
-#define DIMM1 0x51
-#define DIMM2 0x52
-#define DIMM3 0x53
-
 #include "cpu/amd/car/post_cache_as_ram.c"
 
 #include "cpu/amd/model_fxx/init_cpus.c"
diff --git a/src/mainboard/hp/dl145_g3/romstage.c b/src/mainboard/hp/dl145_g3/romstage.c
index ca869d2275..d2e393cbe1 100644
--- a/src/mainboard/hp/dl145_g3/romstage.c
+++ b/src/mainboard/hp/dl145_g3/romstage.c
@@ -92,22 +92,10 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #include "northbridge/amd/amdk8/coherent_ht.c"
 #include "northbridge/amd/amdk8/raminit_f.c"
 #include "lib/generic_sdram.c"
+#include <spd.h>
 
 #include "cpu/amd/dualcore/dualcore.c"
 
-//first node
-#define DIMM0 0x50
-#define DIMM1 0x51
-#define DIMM2 0x52
-#define DIMM3 0x53
-//second node
-#define DIMM4 0x54
-#define DIMM5 0x55
-#define DIMM6 0x56
-#define DIMM7 0x57
-
-
-
 #include "cpu/amd/car/post_cache_as_ram.c"
 
 #include "cpu/amd/model_fxx/init_cpus.c"
diff --git a/src/mainboard/iei/kino-780am2-fam10/romstage.c b/src/mainboard/iei/kino-780am2-fam10/romstage.c
index 6656977bd4..e92f29d26c 100644
--- a/src/mainboard/iei/kino-780am2-fam10/romstage.c
+++ b/src/mainboard/iei/kino-780am2-fam10/romstage.c
@@ -87,17 +87,13 @@ static int spd_read_byte(u32 device, u32 address)
 
 #include "northbridge/amd/amdfam10/early_ht.c"
 #include "southbridge/amd/sb700/sb700_early_setup.c"
+#include <spd.h>
 
 //#include "spd_addr.h"
 
 #define RC00  0
 #define RC01  1
 
-#define DIMM0 0x50
-#define DIMM1 0x51
-#define DIMM2 0x52
-#define DIMM3 0x53
-
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
 
diff --git a/src/mainboard/iei/pcisa-lx-800-r10/romstage.c b/src/mainboard/iei/pcisa-lx-800-r10/romstage.c
index e3351f1294..8412e33170 100644
--- a/src/mainboard/iei/pcisa-lx-800-r10/romstage.c
+++ b/src/mainboard/iei/pcisa-lx-800-r10/romstage.c
@@ -30,6 +30,7 @@
 #include <cpu/amd/lxdef.h>
 #include <cpu/amd/geode_post_code.h>
 #include "southbridge/amd/cs5536/cs5536.h"
+#include <spd.h>
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
 
@@ -50,9 +51,6 @@ static inline int spd_read_byte(unsigned int device, unsigned int address)
 /* Hold Count - how long we will sit in reset */
 #define PLLMSRlo 0x00DE6000
 
-#define DIMM0 0xA0
-#define DIMM1 0xA2
-
 #include "northbridge/amd/lx/raminit.h"
 #include "northbridge/amd/lx/pll_reset.c"
 #include "northbridge/amd/lx/raminit.c"
diff --git a/src/mainboard/intel/truxton/romstage.c b/src/mainboard/intel/truxton/romstage.c
index da48be39b9..105b82115c 100644
--- a/src/mainboard/intel/truxton/romstage.c
+++ b/src/mainboard/intel/truxton/romstage.c
@@ -37,7 +37,7 @@
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "superio/intel/i3100/i3100_early_serial.c"
 #include "cpu/x86/bist.h"
-#include "spd.h"
+#include <spd.h>
 
 #define DEVPRES_CONFIG  (DEVPRES_D1F0 | DEVPRES_D2F0 | DEVPRES_D3F0 | DEVPRES_D4F0)
 
diff --git a/src/mainboard/iwill/dk8_htx/romstage.c b/src/mainboard/iwill/dk8_htx/romstage.c
index c40a69de7c..be3017d27d 100644
--- a/src/mainboard/iwill/dk8_htx/romstage.c
+++ b/src/mainboard/iwill/dk8_htx/romstage.c
@@ -81,15 +81,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #include "resourcemap.c"
 
 #include "cpu/amd/dualcore/dualcore.c"
-
-#define DIMM0 0x50
-#define DIMM1 0x51
-#define DIMM2 0x52
-#define DIMM3 0x53
-#define DIMM4 0x54
-#define DIMM5 0x55
-#define DIMM6 0x56
-#define DIMM7 0x57
+#include <spd.h>
 
 #include "cpu/amd/car/post_cache_as_ram.c"
 
diff --git a/src/mainboard/iwill/dk8s2/romstage.c b/src/mainboard/iwill/dk8s2/romstage.c
index b15643adaa..2d4efe27a1 100644
--- a/src/mainboard/iwill/dk8s2/romstage.c
+++ b/src/mainboard/iwill/dk8s2/romstage.c
@@ -81,15 +81,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #include "northbridge/amd/amdk8/resourcemap.c"
 
 #include "cpu/amd/dualcore/dualcore.c"
-
-#define DIMM0 0x50
-#define DIMM1 0x51
-#define DIMM2 0x52
-#define DIMM3 0x53
-#define DIMM4 0x54
-#define DIMM5 0x55
-#define DIMM6 0x56
-#define DIMM7 0x57
+#include <spd.h>
 
 #include "cpu/amd/car/post_cache_as_ram.c"
 
diff --git a/src/mainboard/iwill/dk8x/romstage.c b/src/mainboard/iwill/dk8x/romstage.c
index b15643adaa..2d4efe27a1 100644
--- a/src/mainboard/iwill/dk8x/romstage.c
+++ b/src/mainboard/iwill/dk8x/romstage.c
@@ -81,15 +81,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #include "northbridge/amd/amdk8/resourcemap.c"
 
 #include "cpu/amd/dualcore/dualcore.c"
-
-#define DIMM0 0x50
-#define DIMM1 0x51
-#define DIMM2 0x52
-#define DIMM3 0x53
-#define DIMM4 0x54
-#define DIMM5 0x55
-#define DIMM6 0x56
-#define DIMM7 0x57
+#include <spd.h>
 
 #include "cpu/amd/car/post_cache_as_ram.c"
 
diff --git a/src/mainboard/jetway/pa78vm5/romstage.c b/src/mainboard/jetway/pa78vm5/romstage.c
index 35cf843692..6944fcc302 100644
--- a/src/mainboard/jetway/pa78vm5/romstage.c
+++ b/src/mainboard/jetway/pa78vm5/romstage.c
@@ -92,17 +92,11 @@ static int spd_read_byte(u32 device, u32 address)
 
 #include "northbridge/amd/amdfam10/early_ht.c"
 #include "southbridge/amd/sb700/sb700_early_setup.c"
-
-
+#include <spd.h>
 
 #define RC00  0
 #define RC01  1
 
-#define DIMM0 0x50
-#define DIMM1 0x51
-#define DIMM2 0x52
-#define DIMM3 0x53
-
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
 
diff --git a/src/mainboard/kontron/kt690/romstage.c b/src/mainboard/kontron/kt690/romstage.c
index 2545b08411..29b2b1477a 100644
--- a/src/mainboard/kontron/kt690/romstage.c
+++ b/src/mainboard/kontron/kt690/romstage.c
@@ -21,9 +21,6 @@
 #define RC0 (6<<8)
 #define RC1 (7<<8)
 
-#define DIMM0 0x50
-#define DIMM1 0x51
-
 #define SMBUS_HUB 0x71
 
 #include <stdint.h>
@@ -40,6 +37,7 @@
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
+#include <spd.h>
 
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"
diff --git a/src/mainboard/lippert/frontrunner/romstage.c b/src/mainboard/lippert/frontrunner/romstage.c
index f86abef5a5..2b3ebe2d85 100644
--- a/src/mainboard/lippert/frontrunner/romstage.c
+++ b/src/mainboard/lippert/frontrunner/romstage.c
@@ -11,15 +11,13 @@
 #include <cpu/amd/gx2def.h>
 #include <cpu/amd/geode_post_code.h>
 #include "southbridge/amd/cs5535/cs5535.h"
+#include <spd.h>
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
 
 #include "southbridge/amd/cs5535/cs5535_early_smbus.c"
 #include "southbridge/amd/cs5535/cs5535_early_setup.c"
 
-#define DIMM0 0xA0
-#define DIMM1 0xFF /* DIMM1 is not available/used on this board. */
-
 static const unsigned char spdbytes[] = {	/* 4x Qimonda HYB25DC512160CF-6 */
 	0xFF, 0xFF,				/* only values used by raminit.c are set */
 	[SPD_MEMORY_TYPE]		= SPD_MEMORY_TYPE_SDRAM_DDR,	/* (Fundamental) memory type */
diff --git a/src/mainboard/lippert/hurricane-lx/romstage.c b/src/mainboard/lippert/hurricane-lx/romstage.c
index b7314bf06f..bc6cae0053 100644
--- a/src/mainboard/lippert/hurricane-lx/romstage.c
+++ b/src/mainboard/lippert/hurricane-lx/romstage.c
@@ -33,6 +33,7 @@
 #include <cpu/amd/lxdef.h>
 #include <cpu/amd/geode_post_code.h>
 #include "southbridge/amd/cs5536/cs5536.h"
+#include <spd.h>
 
 #include "southbridge/amd/cs5536/cs5536_early_smbus.c"
 #include "southbridge/amd/cs5536/cs5536_early_setup.c"
@@ -44,8 +45,6 @@
 #define ManualConf 1		/* No automatic strapped PLL config */
 #define PLLMSRhi 0x0000049C	/* Manual settings for the PLL */
 #define PLLMSRlo 0x00DE6001
-#define DIMM0 0xA0
-#define DIMM1 0xA2
 
 static inline int spd_read_byte(unsigned int device, unsigned int address)
 {
diff --git a/src/mainboard/lippert/literunner-lx/romstage.c b/src/mainboard/lippert/literunner-lx/romstage.c
index 9052cb39c2..38bac67728 100644
--- a/src/mainboard/lippert/literunner-lx/romstage.c
+++ b/src/mainboard/lippert/literunner-lx/romstage.c
@@ -34,6 +34,7 @@
 #include <cpu/amd/lxdef.h>
 #include <cpu/amd/geode_post_code.h>
 #include "southbridge/amd/cs5536/cs5536.h"
+#include <spd.h>
 
 #include "southbridge/amd/cs5536/cs5536_early_smbus.c"
 #include "southbridge/amd/cs5536/cs5536_early_setup.c"
@@ -49,8 +50,6 @@
 #define ManualConf 1		/* No automatic strapped PLL config */
 #define PLLMSRhi 0x0000059C	/* Manual settings for the PLL */
 #define PLLMSRlo 0x00DE6001
-#define DIMM0 0xA0
-#define DIMM1 0xA2
 
 static const unsigned char spdbytes[] = {	// 4x Promos V58C2512164SA-J5I
 	0xFF, 0xFF,				// only values used by Geode-LX raminit.c are set
diff --git a/src/mainboard/lippert/roadrunner-lx/romstage.c b/src/mainboard/lippert/roadrunner-lx/romstage.c
index 11524c4f4c..086a61d8f1 100644
--- a/src/mainboard/lippert/roadrunner-lx/romstage.c
+++ b/src/mainboard/lippert/roadrunner-lx/romstage.c
@@ -33,6 +33,7 @@
 #include <cpu/amd/lxdef.h>
 #include <cpu/amd/geode_post_code.h>
 #include "southbridge/amd/cs5536/cs5536.h"
+#include <spd.h>
 
 #include "southbridge/amd/cs5536/cs5536_early_smbus.c"
 #include "southbridge/amd/cs5536/cs5536_early_setup.c"
@@ -41,8 +42,6 @@
 #define ManualConf 1		/* No automatic strapped PLL config */
 #define PLLMSRhi 0x0000049C	/* Manual settings for the PLL */
 #define PLLMSRlo 0x00DE6001
-#define DIMM0 0xA0
-#define DIMM1 0xA2
 
 static inline int spd_read_byte(unsigned int device, unsigned int address)
 {
diff --git a/src/mainboard/lippert/spacerunner-lx/romstage.c b/src/mainboard/lippert/spacerunner-lx/romstage.c
index 2992bcc9db..cc9e7fda98 100644
--- a/src/mainboard/lippert/spacerunner-lx/romstage.c
+++ b/src/mainboard/lippert/spacerunner-lx/romstage.c
@@ -34,6 +34,7 @@
 #include <cpu/amd/lxdef.h>
 #include <cpu/amd/geode_post_code.h>
 #include "southbridge/amd/cs5536/cs5536.h"
+#include <spd.h>
 
 #include "southbridge/amd/cs5536/cs5536_early_smbus.c"
 #include "southbridge/amd/cs5536/cs5536_early_setup.c"
@@ -49,8 +50,6 @@
 #define ManualConf 1		/* No automatic strapped PLL config */
 #define PLLMSRhi 0x0000059C	/* Manual settings for the PLL */
 #define PLLMSRlo 0x00DE6001
-#define DIMM0 0xA0
-#define DIMM1 0xA2
 
 static const unsigned char spdbytes[] = {	// 4x Promos V58C2512164SA-J5I
 	0xFF, 0xFF,				// only values used by Geode-LX raminit.c are set
diff --git a/src/mainboard/msi/ms9185/romstage.c b/src/mainboard/msi/ms9185/romstage.c
index 0fa6a65d86..74ec60af0a 100644
--- a/src/mainboard/msi/ms9185/romstage.c
+++ b/src/mainboard/msi/ms9185/romstage.c
@@ -93,19 +93,11 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #include "resourcemap.c"
 
 #include "cpu/amd/dualcore/dualcore.c"
+#include <spd.h>
 
 #define RC0 (0x10<<8)
 #define RC1 (0x01<<8)
 
-#define DIMM0 0x50
-#define DIMM1 0x51
-#define DIMM2 0x52
-#define DIMM3 0x53
-#define DIMM4 0x54
-#define DIMM5 0x55
-#define DIMM6 0x56
-#define DIMM7 0x57
-
 #include "cpu/amd/car/post_cache_as_ram.c"
 
 #include "cpu/amd/model_fxx/init_cpus.c"
diff --git a/src/mainboard/pcengines/alix1c/romstage.c b/src/mainboard/pcengines/alix1c/romstage.c
index f0c4ed6325..4b7d0fde04 100644
--- a/src/mainboard/pcengines/alix1c/romstage.c
+++ b/src/mainboard/pcengines/alix1c/romstage.c
@@ -32,6 +32,7 @@
 #include <cpu/amd/lxdef.h>
 #include <cpu/amd/geode_post_code.h>
 #include "southbridge/amd/cs5536/cs5536.h"
+#include <spd.h>
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
 
@@ -106,9 +107,6 @@ static u8 spd_read_byte(u8 device, u8 address)
 #define PLLMSRhi	0x00001490	/* Manual settings for the PLL */
 #define PLLMSRlo	0x02000030
 
-#define DIMM0		0xa0
-#define DIMM1		0xa2
-
 #include "northbridge/amd/lx/raminit.h"
 #include "northbridge/amd/lx/pll_reset.c"
 #include "northbridge/amd/lx/raminit.c"
diff --git a/src/mainboard/pcengines/alix2d/romstage.c b/src/mainboard/pcengines/alix2d/romstage.c
index 10ab27d662..44e14ac7ec 100644
--- a/src/mainboard/pcengines/alix2d/romstage.c
+++ b/src/mainboard/pcengines/alix2d/romstage.c
@@ -32,6 +32,7 @@
 #include <cpu/amd/lxdef.h>
 #include <cpu/amd/geode_post_code.h>
 #include "southbridge/amd/cs5536/cs5536.h"
+#include <spd.h>
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
 
@@ -105,9 +106,6 @@ static u8 spd_read_byte(u8 device, u8 address)
 #define PLLMSRhi	0x00001490	/* Manual settings for the PLL */
 #define PLLMSRlo	0x02000030
 
-#define DIMM0		0xa0
-#define DIMM1		0xa2
-
 #include "northbridge/amd/lx/raminit.h"
 #include "northbridge/amd/lx/pll_reset.c"
 #include "northbridge/amd/lx/raminit.c"
diff --git a/src/mainboard/technexion/tim5690/romstage.c b/src/mainboard/technexion/tim5690/romstage.c
index 05ce74da3a..de86013b5d 100644
--- a/src/mainboard/technexion/tim5690/romstage.c
+++ b/src/mainboard/technexion/tim5690/romstage.c
@@ -20,9 +20,6 @@
 #define RC0 (6<<8)
 #define RC1 (7<<8)
 
-#define DIMM0 0x50
-#define DIMM1 0x51
-
 #define SMBUS_HUB 0x71
 
 #include <stdint.h>
@@ -39,6 +36,7 @@
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
+#include <spd.h>
 
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"
diff --git a/src/mainboard/technexion/tim8690/romstage.c b/src/mainboard/technexion/tim8690/romstage.c
index 44c02fb0c8..c97cd6b4d3 100644
--- a/src/mainboard/technexion/tim8690/romstage.c
+++ b/src/mainboard/technexion/tim8690/romstage.c
@@ -20,9 +20,6 @@
 #define RC0 (6<<8)
 #define RC1 (7<<8)
 
-#define DIMM0 0x50
-#define DIMM1 0x51
-
 #define SMBUS_HUB 0x71
 
 #include <stdint.h>
@@ -39,6 +36,7 @@
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
+#include <spd.h>
 
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"
diff --git a/src/mainboard/traverse/geos/romstage.c b/src/mainboard/traverse/geos/romstage.c
index d5a00a4cbe..b3aff80af4 100644
--- a/src/mainboard/traverse/geos/romstage.c
+++ b/src/mainboard/traverse/geos/romstage.c
@@ -31,6 +31,7 @@
 #include <cpu/amd/lxdef.h>
 #include <cpu/amd/geode_post_code.h>
 #include "southbridge/amd/cs5536/cs5536.h"
+#include <spd.h>
 
 #include "southbridge/amd/cs5536/cs5536_early_smbus.c"
 #include "southbridge/amd/cs5536/cs5536_early_setup.c"
@@ -43,8 +44,6 @@ static inline int spd_read_byte(unsigned int device, unsigned int address)
 #define ManualConf 1		/* Do automatic strapped PLL config */
 #define PLLMSRhi 0x0000059C	/* manual settings for the PLL */
 #define PLLMSRlo 0x00DE602E
-#define DIMM0 0xA0
-#define DIMM1 0xA2
 
 #include "northbridge/amd/lx/raminit.h"
 #include "northbridge/amd/lx/pll_reset.c"
diff --git a/src/mainboard/tyan/s4880/romstage.c b/src/mainboard/tyan/s4880/romstage.c
index 9fc43beb65..157b14a3a6 100644
--- a/src/mainboard/tyan/s4880/romstage.c
+++ b/src/mainboard/tyan/s4880/romstage.c
@@ -84,19 +84,13 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #include "resourcemap.c"
 
 #include "cpu/amd/dualcore/dualcore.c"
+#include <spd.h>
 
 #define RC0 ((1<<2)<<8)
 #define RC1 ((1<<1)<<8)
 #define RC2 ((1<<4)<<8)
 #define RC3 ((1<<3)<<8)
 
-#define DIMM0 0x50
-#define DIMM1 0x51
-#define DIMM2 0x52
-#define DIMM3 0x53
-
-
-
 #include "cpu/amd/car/post_cache_as_ram.c"
 
 #include "cpu/amd/model_fxx/init_cpus.c"
diff --git a/src/mainboard/tyan/s4882/romstage.c b/src/mainboard/tyan/s4882/romstage.c
index f0c94f9b05..ec5e1ddad9 100644
--- a/src/mainboard/tyan/s4882/romstage.c
+++ b/src/mainboard/tyan/s4882/romstage.c
@@ -92,19 +92,13 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #include "resourcemap.c"
 
 #include "cpu/amd/dualcore/dualcore.c"
+#include <spd.h>
 
 #define RC0 ((1<<2)<<8)
 #define RC1 ((1<<1)<<8)
 #define RC2 ((1<<4)<<8)
 #define RC3 ((1<<3)<<8)
 
-#define DIMM0 0x50
-#define DIMM1 0x51
-#define DIMM2 0x52
-#define DIMM3 0x53
-
-
-
 #include "cpu/amd/car/post_cache_as_ram.c"
 
 #include "cpu/amd/model_fxx/init_cpus.c"
diff --git a/src/mainboard/winent/pl6064/romstage.c b/src/mainboard/winent/pl6064/romstage.c
index 76428c5357..6d081e9457 100644
--- a/src/mainboard/winent/pl6064/romstage.c
+++ b/src/mainboard/winent/pl6064/romstage.c
@@ -32,6 +32,7 @@
 #include <cpu/amd/lxdef.h>
 #include <cpu/amd/geode_post_code.h>
 #include "southbridge/amd/cs5536/cs5536.h"
+#include <spd.h>
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
 
@@ -47,8 +48,6 @@ static inline int spd_read_byte(unsigned int device, unsigned int address)
 #define ManualConf 0		/* Do automatic strapped PLL config */
 #define PLLMSRhi 0x00001490	/* Manual settings for the PLL */
 #define PLLMSRlo 0x02000030
-#define DIMM0 0xA0
-#define DIMM1 0xA2
 
 #include "northbridge/amd/lx/raminit.h"
 #include "northbridge/amd/lx/pll_reset.c"
diff --git a/src/mainboard/wyse/s50/romstage.c b/src/mainboard/wyse/s50/romstage.c
index 657667cfe8..d272496462 100644
--- a/src/mainboard/wyse/s50/romstage.c
+++ b/src/mainboard/wyse/s50/romstage.c
@@ -30,13 +30,11 @@
 #include "cpu/x86/msr.h"
 #include <cpu/amd/gx2def.h>
 #include <cpu/amd/geode_post_code.h>
+#include <spd.h>
 
 #include "southbridge/amd/cs5536/cs5536_early_smbus.c"
 #include "southbridge/amd/cs5536/cs5536_early_setup.c"
 
-#define DIMM0 0xA0
-#define DIMM1 0xFF /* DIMM1 is not available/used on this board. */
-
 static inline int spd_read_byte(unsigned int device, unsigned int address)
 {
 	if (device != DIMM0)
diff --git a/src/northbridge/via/cx700/cx700_early_smbus.c b/src/northbridge/via/cx700/cx700_early_smbus.c
index b1d6344f6d..4766e59a29 100644
--- a/src/northbridge/via/cx700/cx700_early_smbus.c
+++ b/src/northbridge/via/cx700/cx700_early_smbus.c
@@ -37,7 +37,6 @@
 
 /* Define register settings */
 #define HOST_RESET		0xff
-#define DIMM_BASE		0xa0	// 1010000 is base for DIMM in SMBus
 #define READ_CMD		0x01	// 1 in the 0 bit of SMBHSTADD states to READ
 
 #define SMBUS_TIMEOUT		(100*1000*10)
diff --git a/src/northbridge/via/vx800/vx800_early_smbus.c b/src/northbridge/via/vx800/vx800_early_smbus.c
index b8a3ef772e..421716cb6c 100644
--- a/src/northbridge/via/vx800/vx800_early_smbus.c
+++ b/src/northbridge/via/vx800/vx800_early_smbus.c
@@ -40,7 +40,6 @@
 
 /* Define register settings */
 #define HOST_RESET	0xff
-#define DIMM_BASE		0xa0	// 1010000 is base for DIMM in SMBus
 #define READ_CMD		0x01	// 1 in the 0 bit of SMBHSTADD states to READ
 
 #define SMBUS_TIMEOUT		(100*1000*10)
@@ -121,9 +120,7 @@ static unsigned int get_spd_data(unsigned int dimm, unsigned int offset)
 	smbus_wait_until_ready();
 
 	/* Do some mathmatic magic */
-	dimm = (dimm << 1);
-	dimm &= 0x0E;
-	dimm |= 0xA0;
+	dimm = (DIMM0 + dimm) << 1;
 
 	outb(dimm | 0x1, SMBXMITADD);
 	outb(offset, SMBHSTCMD);
diff --git a/src/southbridge/amd/cs5536/cs5536_early_smbus.c b/src/southbridge/amd/cs5536/cs5536_early_smbus.c
index ce8e690567..5cb815d250 100644
--- a/src/southbridge/amd/cs5536/cs5536_early_smbus.c
+++ b/src/southbridge/amd/cs5536/cs5536_early_smbus.c
@@ -165,7 +165,7 @@ static unsigned char do_smbus_read_byte(unsigned smbus_io_base,
 		goto err;
 	}
 
-	if ((smbus_send_slave_address(smbus_io_base, device))) {
+	if ((smbus_send_slave_address(smbus_io_base, device << 1))) {
 		error = 3;
 		goto err;
 	}
@@ -182,7 +182,7 @@ static unsigned char do_smbus_read_byte(unsigned smbus_io_base,
 		goto err;
 	}
 
-	if ((smbus_send_slave_address(smbus_io_base, device | 0x01))) {
+	if ((smbus_send_slave_address(smbus_io_base, (device << 1) | 0x01))) {
 		error = 6;
 		goto err;
 	}
diff --git a/src/southbridge/via/vt8231/vt8231_early_smbus.c b/src/southbridge/via/vt8231/vt8231_early_smbus.c
index 8ba72a387b..7bf1267b75 100644
--- a/src/southbridge/via/vt8231/vt8231_early_smbus.c
+++ b/src/southbridge/via/vt8231/vt8231_early_smbus.c
@@ -16,7 +16,6 @@
 
 /* Define register settings */
 #define HOST_RESET 0xff
-#define DIMM_BASE 0xa0		// 1010000 is base for DIMM in SMBus
 #define READ_CMD  0x01		// 1 in the 0 bit of SMBHSTADD states to READ
 
 
diff --git a/src/southbridge/via/vt8235/vt8235_early_smbus.c b/src/southbridge/via/vt8235/vt8235_early_smbus.c
index 1876461a3d..7b9d55dced 100644
--- a/src/southbridge/via/vt8235/vt8235_early_smbus.c
+++ b/src/southbridge/via/vt8235/vt8235_early_smbus.c
@@ -16,7 +16,6 @@
 
 /* Define register settings */
 #define HOST_RESET 0xff
-#define DIMM_BASE 0xa0        // 1010000 is base for DIMM in SMBus
 #define READ_CMD  0x01        // 1 in the 0 bit of SMBHSTADD states to READ