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authorFurquan Shaikh <furquan@google.com>2019-07-06 22:54:53 -0700
committerPatrick Georgi <pgeorgi@google.com>2019-07-07 07:52:06 +0000
commit9eac4c9ddac863344bbe6eab5323e95a266a21e4 (patch)
treeef02f2a9c29d9f8b94c3c14567abece715a73897 /src
parenta913b3df90da925246936cb421afe01901172211 (diff)
downloadcoreboot-9eac4c9ddac863344bbe6eab5323e95a266a21e4.tar.xz
soc/intel/cannonlake, mb/google/sarien: Get rid of unused dev param
This change gets rid of unused dev param to pmc_set_afterg3. BUG=b:136861224 Change-Id: Ic197d6fb8618db15601096f5815e82efc2b539c1 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34117 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Diffstat (limited to 'src')
-rw-r--r--src/mainboard/google/sarien/chromeos.c2
-rw-r--r--src/soc/intel/cannonlake/include/soc/pmc.h3
-rw-r--r--src/soc/intel/cannonlake/pmc.c10
3 files changed, 7 insertions, 8 deletions
diff --git a/src/mainboard/google/sarien/chromeos.c b/src/mainboard/google/sarien/chromeos.c
index fafc469270..7aaf4015b5 100644
--- a/src/mainboard/google/sarien/chromeos.c
+++ b/src/mainboard/google/sarien/chromeos.c
@@ -122,6 +122,6 @@ void mainboard_prepare_cr50_reset(void)
{
#if ENV_RAMSTAGE
/* Ensure system powers up after CR50 reset */
- pmc_set_afterg3(PCH_DEV_PMC, MAINBOARD_POWER_STATE_ON);
+ pmc_set_afterg3(MAINBOARD_POWER_STATE_ON);
#endif
}
diff --git a/src/soc/intel/cannonlake/include/soc/pmc.h b/src/soc/intel/cannonlake/include/soc/pmc.h
index e0d2614e8e..252c719925 100644
--- a/src/soc/intel/cannonlake/include/soc/pmc.h
+++ b/src/soc/intel/cannonlake/include/soc/pmc.h
@@ -171,7 +171,6 @@
#define SCIS_IRQ22 6
#define SCIS_IRQ23 7
-struct device;
-void pmc_set_afterg3(struct device *dev, int s5pwr);
+void pmc_set_afterg3(int s5pwr);
#endif
diff --git a/src/soc/intel/cannonlake/pmc.c b/src/soc/intel/cannonlake/pmc.c
index 0b2356857d..8eb81b0b40 100644
--- a/src/soc/intel/cannonlake/pmc.c
+++ b/src/soc/intel/cannonlake/pmc.c
@@ -32,7 +32,7 @@
* Set which power state system will be after reapplying
* the power (from G3 State)
*/
-void pmc_set_afterg3(struct device *dev, int s5pwr)
+void pmc_set_afterg3(int s5pwr)
{
uint8_t reg8;
uint8_t *pmcbase = pmc_mmio_regs();
@@ -60,7 +60,7 @@ void pmc_set_afterg3(struct device *dev, int s5pwr)
*/
void pmc_soc_restore_power_failure(void)
{
- pmc_set_afterg3(PCH_DEV_PMC, CONFIG_MAINBOARD_POWER_FAILURE_STATE);
+ pmc_set_afterg3(CONFIG_MAINBOARD_POWER_FAILURE_STATE);
}
static void pm1_enable_pwrbtn_smi(void *unused)
@@ -119,7 +119,7 @@ static void config_deep_sx(uint32_t deepsx_config)
write32(pmcbase + DSX_CFG, reg);
}
-static void pch_power_options(struct device *dev)
+static void pch_power_options(void)
{
const char *state;
@@ -144,7 +144,7 @@ static void pch_power_options(struct device *dev)
default:
state = "undefined";
}
- pmc_set_afterg3(dev, pwr_on);
+ pmc_set_afterg3(pwr_on);
printk(BIOS_INFO, "Set power %s after power failure.\n", state);
/* Set up GPE configuration. */
@@ -159,7 +159,7 @@ static void pmc_init(void *unused)
rtc_init();
/* Initialize power management */
- pch_power_options(dev);
+ pch_power_options();
config_deep_s3(config->deep_s3_enable_ac, config->deep_s3_enable_dc);
config_deep_s5(config->deep_s5_enable_ac, config->deep_s5_enable_dc);