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| author | Angel Pons <th3fanbus@gmail.com> | 2020-03-21 18:06:03 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-03-23 19:27:34 +0000 |
| commit | a6a64183d6c5d535df5e62fad419402cd896f03d (patch) | |
| tree | 6bb33bd8f63cb2200ef7afad7b748ffcfb1ee95d /src | |
| parent | 80037f715c9de5a8bb926a0820508d7530e6f429 (diff) | |
| download | coreboot-a6a64183d6c5d535df5e62fad419402cd896f03d.tar.xz | |
nb/intel/sandybridge: Void MRC cache if CPUID differs
Native raminit asserts that the DIMMs haven't been replaced before
reusing the saved training data. However, it does not check if the CPU
is still the same, so it can end up happily reusing data from an Ivy
Bridge CPU onto a Sandy Bridge CPU, which runs the raminit_ivy.c code
path. This can make the CPU run in unsupported configurations, which may
result in an unstable system, or a failure to boot.
To prevent that, ensure that the stored CPUID matches the CPUID of the
installed CPU. If they differ, print a message and do not use the saved
data. As it does not pose a problem for a regular boot, but precludes
resuming from S3, use different loglevels depending on the bootpath.
Tested on Asus P8Z77-V LX2 with an i7-2600 and an i5-3330, works well.
Change-Id: Ib0691f1f849b567579f6afa845c9460e14f8fa27
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39734
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/northbridge/intel/sandybridge/raminit.c | 27 |
1 files changed, 19 insertions, 8 deletions
diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index 2a3e4d73e3..9b524a34eb 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -239,7 +239,7 @@ static void init_dram_ddr3(int min_tck, int s3resume, const u32 cpuid) ramctr_timing ctrl; spd_raw_data spds[4]; struct region_device rdev; - ramctr_timing *ctrl_cached; + ramctr_timing *ctrl_cached = NULL; MCHBAR32(SAPMCTL) |= 1; @@ -266,14 +266,25 @@ static void init_dram_ddr3(int min_tck, int s3resume, const u32 cpuid) /* Try to find timings in MRC cache */ err = mrc_cache_get_current(MRC_TRAINING_DATA, MRC_CACHE_VERSION, &rdev); - if (err || (region_device_sz(&rdev) < sizeof(ctrl))) { - if (s3resume) { - /* Failed S3 resume, reset to come up cleanly */ - system_reset(); - } - ctrl_cached = NULL; - } else { + + if (!err && !(region_device_sz(&rdev) < sizeof(ctrl))) ctrl_cached = rdev_mmap_full(&rdev); + + /* Before reusing training data, assert that the CPU has not been replaced */ + if (ctrl_cached && cpuid != ctrl_cached->cpu) { + + /* It is not really worrying on a cold boot, but fatal when resuming from S3 */ + printk(s3resume ? BIOS_ALERT : BIOS_NOTICE, + "CPUID %x differs from stored CPUID %x, CPU was replaced!\n", + cpuid, ctrl_cached->cpu); + + /* Invalidate the stored data, it likely does not apply to the current CPU */ + ctrl_cached = NULL; + } + + if (s3resume && !ctrl_cached) { + /* S3 resume is impossible, reset to come up cleanly */ + system_reset(); } /* Verify MRC cache for fast boot */ |