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| author | Felix Held <felix-coreboot@felixheld.de> | 2021-02-01 23:27:47 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-02-02 22:50:35 +0000 |
| commit | a7f018a00d7cd156e72c40c100c1d153cdc42e87 (patch) | |
| tree | 99840c5c4696037236053ab5114175eae8e1d45c /src | |
| parent | eb6f80d049c1077bc75fd4288649b3313f7f890e (diff) | |
| download | coreboot-a7f018a00d7cd156e72c40c100c1d153cdc42e87.tar.xz | |
soc/amd/picasso/include/soc/southbridge: remove PM_USB_ENABLE defines
This define was copied over from Stoneyridge, but isn't present on
Picasso and newer.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ideb144c4bff441cf043a647b3f44a65691038eba
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50205
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/amd/picasso/include/soc/southbridge.h | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/src/soc/amd/picasso/include/soc/southbridge.h b/src/soc/amd/picasso/include/soc/southbridge.h index f7edaad9b7..d45c3b04a7 100644 --- a/src/soc/amd/picasso/include/soc/southbridge.h +++ b/src/soc/amd/picasso/include/soc/southbridge.h @@ -74,8 +74,6 @@ #define PM_LPC_AB_NO_BYPASS_EN BIT(2) #define PM_LPC_A20_EN BIT(1) #define PM_LPC_ENABLE BIT(0) -#define PM_USB_ENABLE 0xef -#define PM_USB_ALL_CONTROLLERS 0x7f /* FCH MISC Registers 0xfed80e00 */ #define GPP_CLK_CNTRL 0x00 |