diff options
| author | Tan, Lean Sheng <lean.sheng.tan@intel.com> | 2020-09-03 07:08:53 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-09-08 05:30:44 +0000 |
| commit | aab188174f7fa349ef395ecb38a41d5b6cf45e92 (patch) | |
| tree | 4c2e25753bed32087765353c7f80ac781218c5f4 /src | |
| parent | b369dde9b1cc9daffce83dc809101e0fd0a0e346 (diff) | |
| download | coreboot-aab188174f7fa349ef395ecb38a41d5b6cf45e92.tar.xz | |
soc/intel/elkhartlake: Update SA & PM related definitions
1. Update SA base address & size
2. Update GBE control bit register value
Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com>
Change-Id: I1f5036c9cd75682fcf239170bcb257ffaa002e7d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45077
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/intel/elkhartlake/include/soc/iomap.h | 4 | ||||
| -rw-r--r-- | src/soc/intel/elkhartlake/include/soc/pm.h | 2 |
2 files changed, 3 insertions, 3 deletions
diff --git a/src/soc/intel/elkhartlake/include/soc/iomap.h b/src/soc/intel/elkhartlake/include/soc/iomap.h index 5ba40bc5ff..0246673b03 100644 --- a/src/soc/intel/elkhartlake/include/soc/iomap.h +++ b/src/soc/intel/elkhartlake/include/soc/iomap.h @@ -47,8 +47,8 @@ #define VTD_BASE_ADDRESS 0xfed90000 #define VTD_BASE_SIZE 0x00004000 -#define MCH_BASE_ADDRESS 0xfea80000 -#define MCH_BASE_SIZE 0x8000 +#define MCH_BASE_ADDRESS 0xfec80000 +#define MCH_BASE_SIZE 0x80000 #define EARLY_GSPI_BASE_ADDRESS 0xfe011000 diff --git a/src/soc/intel/elkhartlake/include/soc/pm.h b/src/soc/intel/elkhartlake/include/soc/pm.h index 11d6663b74..6ebbbfa170 100644 --- a/src/soc/intel/elkhartlake/include/soc/pm.h +++ b/src/soc/intel/elkhartlake/include/soc/pm.h @@ -65,7 +65,7 @@ #define SMI_ON_SLP_EN_STS_BIT 4 #define LEGACY_USB_STS_BIT 3 #define BIOS_STS_BIT 2 -#define GPE_CNTL 0x42 +#define GPE_CNTL 0x40 #define SWGPE_CTRL (1 << 1) #define DEVACT_STS 0x44 #define PM2_CNT 0x50 |