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authorAngel Pons <th3fanbus@gmail.com>2020-08-10 13:08:47 +0200
committerAngel Pons <th3fanbus@gmail.com>2020-08-12 10:54:30 +0000
commitab6ecb4d08233656a549d0f70e52d079946119f6 (patch)
tree9774eabbba8f9726acbf364cd66d394908a7fc79 /src
parentbfb3b460ed5c4a91ba77405feb6626dcda8f8492 (diff)
downloadcoreboot-ab6ecb4d08233656a549d0f70e52d079946119f6.tar.xz
sb/intel/bd82x6x: Remove incorrect RCBA registers
These were probably copy-pasted from some ICHx southbridge, and then some were corrected because native PCH init uses them. Delete the definitions which are unused and are invalid for this southbridge. Change-Id: I0be72f76c7fcc63316ae8566891e0732456a8c55 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44329 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src')
-rw-r--r--src/southbridge/intel/bd82x6x/pch.h20
1 files changed, 0 insertions, 20 deletions
diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h
index 75529065f8..68f599d914 100644
--- a/src/southbridge/intel/bd82x6x/pch.h
+++ b/src/southbridge/intel/bd82x6x/pch.h
@@ -229,26 +229,6 @@ void early_usb_init(const struct southbridge_usb_port *portmap);
#define CIR0 0x0050 /* 32bit */
#define TCLOCKDN (1u << 31)
-#define RCTCL 0x0100 /* 32bit */
-#define ESD 0x0104 /* 32bit */
-#define ULD 0x0110 /* 32bit */
-#define ULBA 0x0118 /* 64bit */
-
-#define RP1D 0x0120 /* 32bit */
-#define RP1BA 0x0128 /* 64bit */
-#define RP2D 0x0130 /* 32bit */
-#define RP2BA 0x0138 /* 64bit */
-#define RP3D 0x0140 /* 32bit */
-#define RP3BA 0x0148 /* 64bit */
-#define RP4D 0x0150 /* 32bit */
-#define RP4BA 0x0158 /* 64bit */
-#define HDD 0x0160 /* 32bit */
-#define HDBA 0x0168 /* 64bit */
-#define RP5D 0x0170 /* 32bit */
-#define RP5BA 0x0178 /* 64bit */
-#define RP6D 0x0180 /* 32bit */
-#define RP6BA 0x0188 /* 64bit */
-
#define RPC 0x0400 /* 32bit */
#define RPFN 0x0404 /* 32bit */