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authorMarshall Dawson <marshalldawson3rd@gmail.com>2018-10-12 10:22:33 -0600
committerMartin Roth <martinroth@google.com>2018-10-14 19:11:48 +0000
commitafaedc96c838e4115b2a5a53f3aa5ad4e6103aa3 (patch)
treefa9b073f2d8bdbac5209c2a3959153761ca5a77d /src
parentfdff6c25a1ff4aa7ca63f32157ca3def5e622dea (diff)
downloadcoreboot-afaedc96c838e4115b2a5a53f3aa5ad4e6103aa3.tar.xz
soc/amd/stoneyridge: Remove hudson EHCI debug controllers
Remove nonpreset controllers from the PCI device identifier function (ignoring any CONFIG_USBDEBUG_HCD_INDEX). The extra devices appear to be holdovers from the original sb/hudson source. TEST=Jam Makefile.inc to unconditionally build enable_usbdebug.c and verify proper BDF is returned in romstage and ramstage. Change-Id: I2e819d5e998922ad427c4a094c29a590f249a0d3 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/29074 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src')
-rw-r--r--src/soc/amd/stoneyridge/enable_usbdebug.c8
1 files changed, 2 insertions, 6 deletions
diff --git a/src/soc/amd/stoneyridge/enable_usbdebug.c b/src/soc/amd/stoneyridge/enable_usbdebug.c
index 5220457e45..0a0c3ec66d 100644
--- a/src/soc/amd/stoneyridge/enable_usbdebug.c
+++ b/src/soc/amd/stoneyridge/enable_usbdebug.c
@@ -20,6 +20,7 @@
#include <arch/io.h>
#include <device/pci_ehci.h>
#include <device/pci_def.h>
+#include <soc/pci_devs.h>
#include <soc/southbridge.h>
pci_devfn_t pci_ehci_dbg_dev(unsigned int hcd_idx)
@@ -28,12 +29,7 @@ pci_devfn_t pci_ehci_dbg_dev(unsigned int hcd_idx)
outb(0xef, PM_INDEX);
outb(0x7f, PM_DATA);
- if (hcd_idx == 3)
- return PCI_DEV(0, 0x16, 0);
- else if (hcd_idx == 2)
- return PCI_DEV(0, 0x13, 0);
- else
- return PCI_DEV(0, 0x12, 0);
+ return SOC_EHCI1_DEV;
}
void pci_ehci_dbg_set_port(pci_devfn_t dev, unsigned int port)