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authorAngel Pons <th3fanbus@gmail.com>2020-07-07 17:36:08 +0200
committerAngel Pons <th3fanbus@gmail.com>2020-07-25 10:18:34 +0000
commitb046bfa8307edb4e1ff38fad283fc8e589762758 (patch)
tree1a8082e526cc64c4e95b9811cf2bbec0452733dd /src
parent06e44a862e2154b7fd77f627634f7a0cf27eb066 (diff)
downloadcoreboot-b046bfa8307edb4e1ff38fad283fc8e589762758.tar.xz
soc/intel/baytrail/cpu.c: Align with Braswell
This reduces the differences between Bay Trail and Braswell. Tested with BUILD_TIMELESS=1, Google Ninja remains identical. Change-Id: I52d58c6b77cd870b5d3f5892521e4c82027c4cac Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43190 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
-rw-r--r--src/soc/intel/baytrail/cpu.c24
1 files changed, 11 insertions, 13 deletions
diff --git a/src/soc/intel/baytrail/cpu.c b/src/soc/intel/baytrail/cpu.c
index d91c3589b2..f745b32b1f 100644
--- a/src/soc/intel/baytrail/cpu.c
+++ b/src/soc/intel/baytrail/cpu.c
@@ -23,8 +23,8 @@
const struct reg_script core_msr_script[] = {
/* Dynamic L2 shrink enable and threshold, clear SINGLE_PCTL bit 11 */
REG_MSR_RMW(MSR_PKG_CST_CONFIG_CONTROL, ~0x3f080f, 0xe0008),
- REG_MSR_RMW(MSR_POWER_MISC,
- ~(ENABLE_ULFM_AUTOCM_MASK | ENABLE_INDP_AUTOCM_MASK), 0),
+ REG_MSR_RMW(MSR_POWER_MISC, ~(ENABLE_ULFM_AUTOCM_MASK | ENABLE_INDP_AUTOCM_MASK), 0),
+
/* Disable C1E */
REG_MSR_RMW(MSR_POWER_CTL, ~0x2, 0),
REG_MSR_OR(MSR_POWER_MISC, 0x44),
@@ -165,8 +165,7 @@ static void per_cpu_smm_trigger(void)
intel_microcode_load_unlocked(pattrs->microcode_patch);
}
-static void relocation_handler(int cpu, uintptr_t curr_smbase,
- uintptr_t staggered_smbase)
+static void relocation_handler(int cpu, uintptr_t curr_smbase, uintptr_t staggered_smbase)
{
struct smm_relocation_params *relo_params = &smm_reloc_params;
em64t100_smm_state_save_area_t *smm_state;
@@ -185,21 +184,20 @@ static void post_mp_init(void)
}
static const struct mp_ops mp_ops = {
- .pre_mp_init = pre_mp_init,
- .get_cpu_count = get_cpu_count,
- .get_smm_info = get_smm_info,
- .get_microcode_info = get_microcode_info,
- .pre_mp_smm_init = smm_southbridge_clear_state,
+ .pre_mp_init = pre_mp_init,
+ .get_cpu_count = get_cpu_count,
+ .get_smm_info = get_smm_info,
+ .get_microcode_info = get_microcode_info,
+ .pre_mp_smm_init = smm_southbridge_clear_state,
.per_cpu_smm_trigger = per_cpu_smm_trigger,
- .relocation_handler = relocation_handler,
- .post_mp_init = post_mp_init,
+ .relocation_handler = relocation_handler,
+ .post_mp_init = post_mp_init,
};
void baytrail_init_cpus(struct device *dev)
{
struct bus *cpu_bus = dev->link_list;
- if (mp_init_with_smm(cpu_bus, &mp_ops)) {
+ if (mp_init_with_smm(cpu_bus, &mp_ops))
printk(BIOS_ERR, "MP initialization failure.\n");
- }
}