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| author | Vladimir Serbinenko <phcoder@gmail.com> | 2015-01-31 17:45:50 +0100 |
|---|---|---|
| committer | Vladimir Serbinenko <phcoder@gmail.com> | 2015-02-01 08:22:40 +0100 |
| commit | b26156ec65f1622f97d4439b3977c7880f234054 (patch) | |
| tree | a44a0ad552e90400b51c7c8a4c96aade6bec928e /src | |
| parent | e1e11e63afab8e461ac7e6466c9a7f9f47a10702 (diff) | |
| download | coreboot-b26156ec65f1622f97d4439b3977c7880f234054.tar.xz | |
bd82x6x/xhci: Set mask of ports switchable between USB2 and USB3.
Change-Id: Ica1cc90715c1810668e3f4f7282e5757a5688483
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/8312
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/southbridge/intel/bd82x6x/chip.h | 5 | ||||
| -rw-r--r-- | src/southbridge/intel/bd82x6x/usb_xhci.c | 4 |
2 files changed, 9 insertions, 0 deletions
diff --git a/src/southbridge/intel/bd82x6x/chip.h b/src/southbridge/intel/bd82x6x/chip.h index 290bb058ac..f4be82d81f 100644 --- a/src/southbridge/intel/bd82x6x/chip.h +++ b/src/southbridge/intel/bd82x6x/chip.h @@ -89,6 +89,11 @@ struct southbridge_intel_bd82x6x_config { int docking_supported; uint8_t pcie_hotplug_map[8]; + + /* Ports which can be routed to either EHCI or xHCI. */ + uint32_t xhci_switchable_ports; + /* Ports which support SuperSpeed (USB 3.0 additional lanes). */ + uint32_t superspeed_capable_ports; }; #endif /* SOUTHBRIDGE_INTEL_BD82X6X_CHIP_H */ diff --git a/src/southbridge/intel/bd82x6x/usb_xhci.c b/src/southbridge/intel/bd82x6x/usb_xhci.c index 19c419facb..eb89a7d64f 100644 --- a/src/southbridge/intel/bd82x6x/usb_xhci.c +++ b/src/southbridge/intel/bd82x6x/usb_xhci.c @@ -29,6 +29,7 @@ static void usb_xhci_init(struct device *dev) { u32 reg32; + struct southbridge_intel_bd82x6x_config *config = dev->chip_info; printk(BIOS_DEBUG, "XHCI: Setting up controller.. "); @@ -37,6 +38,9 @@ static void usb_xhci_init(struct device *dev) reg32 |= 1; pci_write_config32(dev, 0x44, reg32); + pci_write_config32(dev, 0xd4, config->xhci_switchable_ports); + pci_write_config32(dev, 0xdc, config->superspeed_capable_ports); + /* Enable clock gating */ reg32 = pci_read_config32(dev, 0x40); reg32 &= ~((1 << 20) | (1 << 21)); |