diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2020-03-17 23:46:53 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2020-03-22 15:21:58 +0000 |
| commit | b3884dc59b3f84091136fbff0b8a790e1a4b91f3 (patch) | |
| tree | 09b112ee9e7d2d5cf1cd8c186e3ea134eee6fde6 /src | |
| parent | cf8602b453d4e193ce71a0452fac2b769c881b23 (diff) | |
| download | coreboot-b3884dc59b3f84091136fbff0b8a790e1a4b91f3.tar.xz | |
nb/intel/sandybridge: Drop spurious register write
It does not make sense to disable an optimization that was not enabled
before, especially if that optimization only applies to Ivy Bridge.
Tested, still boots and can suspend correctly with:
- Asus P8Z77-V LX2 with i5-3330 and Windows 10
- Gigabyte GA-H61MA-D3V with i5-2400 and Arch Linux
Change-Id: I9f3eb545585824bbdf51e33f0592e7daa1c425af
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39623
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src')
| -rw-r--r-- | src/northbridge/intel/sandybridge/raminit_common.c | 7 |
1 files changed, 0 insertions, 7 deletions
diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 2cb6a8337b..e28907086d 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -3236,11 +3236,4 @@ void restore_timings(ramctr_timing *ctrl) MCHBAR32_AND(GDCRCMDDEBUGMUXCFG_Cz_S(channel), ~0x3f000000); udelay(2); } - - /* - * Disable IOSAV_n_SPECIAL_COMMAND_ADDR optimization. - * FIXME: This must only be done on Ivy Bridge. Moreover, this instance seems to be - * spurious, because nothing else enabled this optimization before. - */ - MCHBAR32(MCMNTS_SPARE) = 0; } |