diff options
| author | Vadim Bendebury <vbendeb@chromium.org> | 2016-07-13 23:12:27 -0700 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-07-18 20:14:07 +0200 |
| commit | b4d3d09ded8bbb72007bd4429d32b9b2c6d715a9 (patch) | |
| tree | 586ffa12bc117386b03fa3b8fce249d4efc477b1 /src | |
| parent | e19d9af9eed7540f52d39d746314877ab6e0bfe5 (diff) | |
| download | coreboot-b4d3d09ded8bbb72007bd4429d32b9b2c6d715a9.tar.xz | |
gru: implement hw reset function
Asserting this GPIO will send a signal to the EC to trigger a reset
for the AP and the CR50.
BRANCH=none
BUG=chrome-os-partner:55252
TEST=the device now reboots when it needs to switch between different
boot modes instead of hanging with "failed to reboot" message.
Change-Id: I8d168e313b6983c96c80f7ad6d70bb84c1ec1d9c
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id: 83a4c8ff68ab24a103f2166e948eb23624ea97f7
Original-Change-Id: Idfd20977cf3682bd8933f89e8eec53005e55864e
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/360238
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/15718
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src')
| -rw-r--r-- | src/mainboard/google/gru/Makefile.inc | 2 | ||||
| -rw-r--r-- | src/mainboard/google/gru/reset.c | 7 | ||||
| -rw-r--r-- | src/soc/rockchip/rk3399/Makefile.inc | 2 |
3 files changed, 8 insertions, 3 deletions
diff --git a/src/mainboard/google/gru/Makefile.inc b/src/mainboard/google/gru/Makefile.inc index 9e87fadd1c..a0839e0207 100644 --- a/src/mainboard/google/gru/Makefile.inc +++ b/src/mainboard/google/gru/Makefile.inc @@ -16,7 +16,6 @@ bootblock-y += bootblock.c bootblock-y += chromeos.c bootblock-y += memlayout.ld -bootblock-y += reset.c verstage-y += chromeos.c verstage-y += memlayout.ld @@ -25,7 +24,6 @@ verstage-y += reset.c romstage-y += boardid.c romstage-y += chromeos.c romstage-y += memlayout.ld -romstage-y += reset.c romstage-y += sdram_configs.c ramstage-y += boardid.c diff --git a/src/mainboard/google/gru/reset.c b/src/mainboard/google/gru/reset.c index 31d8b3de2d..bd06923532 100644 --- a/src/mainboard/google/gru/reset.c +++ b/src/mainboard/google/gru/reset.c @@ -13,9 +13,14 @@ * GNU General Public License for more details. */ -#include <arch/io.h> +#include <gpio.h> #include <reset.h> +#include "board.h" + void hard_reset(void) { + gpio_output(GPIO_RESET, 1); + while (1) + ; } diff --git a/src/soc/rockchip/rk3399/Makefile.inc b/src/soc/rockchip/rk3399/Makefile.inc index 28c633835a..7a5e7a1e7a 100644 --- a/src/soc/rockchip/rk3399/Makefile.inc +++ b/src/soc/rockchip/rk3399/Makefile.inc @@ -29,6 +29,8 @@ bootblock-y += mmu_operations.c bootblock-y += timer.c verstage-y += ../common/cbmem.c +verstage-y += ../common/gpio.c +verstage-y += gpio.c verstage-y += sdram.c verstage-y += ../common/spi.c verstage-$(CONFIG_DRIVERS_UART) += ../common/uart.c |