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| author | Arthur Heymans <arthur@aheymans.xyz> | 2021-04-30 16:11:37 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-05-05 11:46:43 +0000 |
| commit | b761903b8bbcf33b1f159b7899e0970f2eac6498 (patch) | |
| tree | cfd3d549e0abacea4d91795be9c3382a6c1c34b2 /src | |
| parent | c37d7b979f25332f8dec63cd70e7d8c39eef325d (diff) | |
| download | coreboot-b761903b8bbcf33b1f159b7899e0970f2eac6498.tar.xz | |
sb/intel/lynxpoint: Fix VBOOT with !CONFIG_INTEL_LYNXPOINT_LP
The Intel Basking Ridge CRB does not have a Lynxpoint LP PCH but was
using the lp gpio code instead of the southbridge/intel/common code in
verstage.
Change-Id: I775d3dc3540fbd8a939701d873183dd016e24ba4
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52790
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/southbridge/intel/common/Makefile.inc | 1 | ||||
| -rw-r--r-- | src/southbridge/intel/lynxpoint/Makefile.inc | 2 |
2 files changed, 2 insertions, 1 deletions
diff --git a/src/southbridge/intel/common/Makefile.inc b/src/southbridge/intel/common/Makefile.inc index adacc25a4b..1fc3a63066 100644 --- a/src/southbridge/intel/common/Makefile.inc +++ b/src/southbridge/intel/common/Makefile.inc @@ -27,6 +27,7 @@ romstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG) += usb_debug.c ramstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG) += usb_debug.c bootblock-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO) += gpio.c +verstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO) += gpio.c romstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO) += gpio.c ramstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO) += gpio.c smm-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO) += gpio.c diff --git a/src/southbridge/intel/lynxpoint/Makefile.inc b/src/southbridge/intel/lynxpoint/Makefile.inc index f980a6554d..9ffd764764 100644 --- a/src/southbridge/intel/lynxpoint/Makefile.inc +++ b/src/southbridge/intel/lynxpoint/Makefile.inc @@ -41,10 +41,10 @@ ifeq ($(CONFIG_INTEL_LYNXPOINT_LP),y) romstage-y += lp_gpio.c ramstage-y += lp_gpio.c smm-y += lp_gpio.c +verstage-$(CONFIG_VBOOT_SEPARATE_VERSTAGE) += lp_gpio.c endif verstage-$(CONFIG_VBOOT_SEPARATE_VERSTAGE) += pmutil.c -verstage-$(CONFIG_VBOOT_SEPARATE_VERSTAGE) += lp_gpio.c CPPFLAGS_common += -I$(src)/southbridge/intel/lynxpoint/include |