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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2020-06-23 21:36:14 +0300 |
|---|---|---|
| committer | Hung-Te Lin <hungte@chromium.org> | 2020-12-28 13:37:15 +0000 |
| commit | b8cb142ccd1922f8f0a245923eabaed5030048e5 (patch) | |
| tree | 9c6c2095eb61fa74a97e92c65faab5315a46d9c0 /src | |
| parent | 219caf83580a86acf073f73662356a078bd96244 (diff) | |
| download | coreboot-b8cb142ccd1922f8f0a245923eabaed5030048e5.tar.xz | |
sb/amd/pi/hudson: Enable use of common GPIO API
The code in soc/amd/common has an implementation of
GPIO register space that is compatible with the hardware
sb/amd/pi/hudson supports.
Change-Id: I86ae40a3cdf335263d7e9e3dcfdd588947cdd9b1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42733
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src')
| -rw-r--r-- | src/southbridge/amd/pi/hudson/Kconfig | 1 | ||||
| -rw-r--r-- | src/southbridge/amd/pi/hudson/soc/gpio.h | 9 | ||||
| -rw-r--r-- | src/southbridge/amd/pi/hudson/soc/smi.h | 11 | ||||
| -rw-r--r-- | src/vendorcode/amd/pi/Makefile.inc | 2 |
4 files changed, 22 insertions, 1 deletions
diff --git a/src/southbridge/amd/pi/hudson/Kconfig b/src/southbridge/amd/pi/hudson/Kconfig index c87d7a0904..6280f3acd0 100644 --- a/src/southbridge/amd/pi/hudson/Kconfig +++ b/src/southbridge/amd/pi/hudson/Kconfig @@ -19,6 +19,7 @@ config SOUTHBRIDGE_SPECIFIC_OPTIONS # dummy select HAVE_CF9_RESET_PREPARE select SOC_AMD_COMMON select SOC_AMD_COMMON_BLOCK_ACPIMMIO + select SOC_AMD_COMMON_BLOCK_BANKED_GPIOS select SOC_AMD_COMMON_BLOCK_PCI_MMCONF config EHCI_BAR diff --git a/src/southbridge/amd/pi/hudson/soc/gpio.h b/src/southbridge/amd/pi/hudson/soc/gpio.h new file mode 100644 index 0000000000..10a47cb101 --- /dev/null +++ b/src/southbridge/amd/pi/hudson/soc/gpio.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOC_GPIO_H +#define SOC_GPIO_H + +/* <soc/gpio.h> must provide gpio_t. */ +#include <amdblocks/gpio_banks.h> + +#endif /* SOC_GPIO_H */ diff --git a/src/southbridge/amd/pi/hudson/soc/smi.h b/src/southbridge/amd/pi/hudson/soc/smi.h new file mode 100644 index 0000000000..da5ddbc2f7 --- /dev/null +++ b/src/southbridge/amd/pi/hudson/soc/smi.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOC_SMI_H +#define SOC_SMI_H + +#define SMI_SCI_TRIG 0x08 +#define SMI_SCI_LEVEL 0x0c +#define SMI_SCI_STATUS 0x10 +#define SMI_SCI_EN 0x14 + +#endif /* SOC_SMI_H */ diff --git a/src/vendorcode/amd/pi/Makefile.inc b/src/vendorcode/amd/pi/Makefile.inc index 25e3652751..47db4e108e 100644 --- a/src/vendorcode/amd/pi/Makefile.inc +++ b/src/vendorcode/amd/pi/Makefile.inc @@ -76,7 +76,7 @@ export AGESA_CFLAGS := $(AGESA_CFLAGS) CC_bootblock := $(CC_bootblock) $(AGESA_INC) $(AGESA_CFLAGS) CC_romstage := $(CC_romstage) $(AGESA_INC) $(AGESA_CFLAGS) -CC_postcar:= $(CC_postcar) -I$(AGESA_ROOT)/binaryPI +CC_postcar:= $(CC_postcar) -I$(src)/southbridge/amd/pi/hudson -I$(AGESA_ROOT)/binaryPI CC_ramstage := $(CC_ramstage) $(AGESA_INC) $(AGESA_CFLAGS) CC_x86_32 := $(CC_x86_32) $(AGESA_INC) $(AGESA_CFLAGS) |