diff options
| author | Yen Lin <yelin@nvidia.com> | 2014-07-10 14:11:16 -0700 |
|---|---|---|
| committer | Marc Jones <marc.jones@se-eng.com> | 2015-02-17 01:16:55 +0100 |
| commit | ba118cc3a92ecf4b5334ddb8b2057319cc05950d (patch) | |
| tree | 830afd6a339f9efe81586e1811189d84c3452605 /src | |
| parent | 5840626cec3db3262d506c0f90d062b8c602f3ea (diff) | |
| download | coreboot-ba118cc3a92ecf4b5334ddb8b2057319cc05950d.tar.xz | |
T124: perform ram_repair when CPU rail is powered on in warmboot
This patch is to perform software triggered RAM re-repair in
the warm boot path.
"RAM" actually refers to the CPU cache here (yeah, I know, but that's
how the manuals call it). This is some magic hardware thing that must be
done every time after applying power to the main CPU cores or their
cache may have random failures in some very rare cases.
Also, note that this file isn't built in coreboot proper, but is a
companion binary for kernel. It resides here for safe keeping.
BUG=chrome-os-partner:30430
BRANCH=nyan
TEST=run suspend_stress_test on nyan.
Original-Signed-off-by: Yen Lin <yelin@nvidia.com>
Original-Change-Id: I540f8afbffa323d1e378cb6ba6a20be4afd08339
Original-Reviewed-on: https://chromium-review.googlesource.com/207422
Original-Tested-by: Yen Lin <yelin@nvidia.com>
Original-Reviewed-by: Tom Warren <twarren@nvidia.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-by: Andrew Bresticker <abrestic@chromium.org>
Original-Commit-Queue: Yen Lin <yelin@nvidia.com>
(cherry picked from commit f06c413c42819f8f75d9b0fecde02b82583f1d2a)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I151ce943ce8623e46cc55f890bbd6fc641cc2b98
Reviewed-on: http://review.coreboot.org/8416
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c | 29 |
1 files changed, 29 insertions, 0 deletions
diff --git a/src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c b/src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c index 9b1a4b5562..0a3cb48641 100644 --- a/src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c +++ b/src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c @@ -193,6 +193,14 @@ enum { FLOW_CLUSTER_ACTIVE_LP = 0x1 << 0 }; +static uint32_t *flow_ctlr_ram_repair_ptr = + (void *)(FLOW_CTLR_BASE + 0x40); +static uint32_t *flow_ctlr_ram_repair_cluster1_ptr = + (void *)(FLOW_CTLR_BASE + 0x58); +enum { + RAM_REPAIR_REQ = 0x1 << 0, + RAM_REPAIR_STS = 0x1 << 1, +}; /* Power management controller registers. */ @@ -483,6 +491,24 @@ static void clear_cpu_resets(void) +/* RAM repair */ + +void ram_repair(void) +{ + // Request Cluster0 RAM repair. + setbits32(RAM_REPAIR_REQ, flow_ctlr_ram_repair_ptr); + // Poll for Cluster0 RAM repair status. + while (!(read32(flow_ctlr_ram_repair_ptr) & RAM_REPAIR_STS)) + ; + + // Request Cluster1 RAM repair. + setbits32(RAM_REPAIR_REQ, flow_ctlr_ram_repair_cluster1_ptr); + // Poll for Cluster1 RAM repair status. + while (!(read32(flow_ctlr_ram_repair_cluster1_ptr) & RAM_REPAIR_STS)) + ; +} + + /* Power. */ static void power_on_partition(unsigned id) @@ -589,6 +615,9 @@ void lp0_resume(void) power_on_main_cpu(); + // Perform ram repair after cpu is powered on. + ram_repair(); + clear_cpu_resets(); // Halt the AVP. |