diff options
| author | Stefan Reinauer <stepan@coresystems.de> | 2010-08-25 18:35:42 +0000 |
|---|---|---|
| committer | Stefan Reinauer <stepan@openbios.org> | 2010-08-25 18:35:42 +0000 |
| commit | bc8613ecaf858419288f4cef784c562f3d8a5093 (patch) | |
| tree | 767aeddf79a40354af772f1800c8629651b03857 /src | |
| parent | 6f22ecc2c920b41f5c48d96030333d1874f67c8d (diff) | |
| download | coreboot-bc8613ecaf858419288f4cef784c562f3d8a5093.tar.xz | |
Fix i945 based boards
- prevent GCC from inlining do_ram_command - it will break RAM initialization.
- fix the PCIRST# mechanism in those boards that do it, it requires 200ms, not
200us
- move PCIRST# as early as possible (before ich7_enable_lpc)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Corey Osgood <corey.osgood@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5740 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src')
| -rw-r--r-- | src/mainboard/getac/p470/romstage.c | 3 | ||||
| -rw-r--r-- | src/mainboard/kontron/986lcd-m/romstage.c | 6 | ||||
| -rw-r--r-- | src/mainboard/roda/rk886ex/romstage.c | 5 | ||||
| -rw-r--r-- | src/northbridge/intel/i945/raminit.c | 2 |
4 files changed, 7 insertions, 9 deletions
diff --git a/src/mainboard/getac/p470/romstage.c b/src/mainboard/getac/p470/romstage.c index 451f5d9d8a..9f7c14af52 100644 --- a/src/mainboard/getac/p470/romstage.c +++ b/src/mainboard/getac/p470/romstage.c @@ -308,9 +308,8 @@ void main(unsigned long bist) #if 0 /* Force PCIRST# */ pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, SBR); - udelay(200); + udelay(200 * 1000); pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, 0); - udelay(200); #endif ich7_enable_lpc(); diff --git a/src/mainboard/kontron/986lcd-m/romstage.c b/src/mainboard/kontron/986lcd-m/romstage.c index 5faf699129..902e5c2679 100644 --- a/src/mainboard/kontron/986lcd-m/romstage.c +++ b/src/mainboard/kontron/986lcd-m/romstage.c @@ -366,14 +366,12 @@ void main(unsigned long bist) enable_lapic(); } - ich7_enable_lpc(); - /* Force PCIRST# */ pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, SBR); - udelay(200); + udelay(200 * 1000); pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, 0); - udelay(200); + ich7_enable_lpc(); early_superio_config_w83627thg(); /* Set up the console */ diff --git a/src/mainboard/roda/rk886ex/romstage.c b/src/mainboard/roda/rk886ex/romstage.c index 19b29053e3..00c4c9f446 100644 --- a/src/mainboard/roda/rk886ex/romstage.c +++ b/src/mainboard/roda/rk886ex/romstage.c @@ -279,11 +279,12 @@ void main(unsigned long bist) enable_lapic(); } - ich7_enable_lpc(); - /* Force PCIRST# */ pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, SBR); + udelay(200 * 1000); + pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, 0); + ich7_enable_lpc(); early_superio_config(); /* Set up the console */ diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index b05a553c5a..23390cffb6 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -45,7 +45,7 @@ #define RAM_EMRS_2 (0x1 << 21) #define RAM_EMRS_3 (0x2 << 21) -static void do_ram_command(u32 command) +static __attribute__((noinline)) void do_ram_command(u32 command) { u32 reg32; |