diff options
| author | David Hendricks <dhendrix@chromium.org> | 2013-08-08 16:04:07 -0700 |
|---|---|---|
| committer | Patrick Georgi <patrick@georgi-clan.de> | 2013-12-21 22:46:24 +0100 |
| commit | bd56bf0dcff59d38066715438a9350f50136fcc3 (patch) | |
| tree | a5926330c971e22aad358a3d9ec25adce2d7491b /src | |
| parent | 136e7090152d91ad0e1efcf4869e23fbaa6f453c (diff) | |
| download | coreboot-bd56bf0dcff59d38066715438a9350f50136fcc3.tar.xz | |
exynos5420: correct the PMS value for CPLL
This patch matches the User Manual Table 7-2 about the PMS value for
CPLL. This doesn't change the PLL frequency (before and after both make
666MHz) but this is the suggested PMSK values for obtaining 666.
(Suggested as per user manual).
This is ported from https://gerrit.chromium.org/gerrit/#/c/62438/
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Change-Id: Ia33e1971ab88da761000d443792560476514626b
Reviewed-on: https://gerrit.chromium.org/gerrit/65281
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Commit-Queue: David Hendricks <dhendrix@chromium.org>
Tested-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/4460
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Diffstat (limited to 'src')
| -rw-r--r-- | src/cpu/samsung/exynos5420/clock_init.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/cpu/samsung/exynos5420/clock_init.c b/src/cpu/samsung/exynos5420/clock_init.c index 352163619c..07bf5d95c2 100644 --- a/src/cpu/samsung/exynos5420/clock_init.c +++ b/src/cpu/samsung/exynos5420/clock_init.c @@ -113,7 +113,7 @@ void system_clock_init(void) /* Set CPLL */ writel(CPLL_CON1_VAL, &clk->cpll_con1); - val = set_pll(0x6f, 0x2, 0x1); + val = set_pll(0xde, 0x4, 0x1); writel(val, &clk->cpll_con0); while ((readl(&clk->cpll_con0) & PLL_LOCKED) == 0) ; |