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authorFurquan Shaikh <furquan@google.com>2016-06-19 23:20:08 -0700
committerFurquan Shaikh <furquan@google.com>2016-06-21 20:38:15 +0200
commitbdcda710a7e4bc439408eedaf3e66145c6831c90 (patch)
tree168cf4e271771573aeab0ec0d707b545b88212c1 /src
parentd3f4c5be8b52638a55997a7d5b6254c39be47830 (diff)
downloadcoreboot-bdcda710a7e4bc439408eedaf3e66145c6831c90.tar.xz
intel/apollolake: Add helper routine for spi reg read
BUG=chrome-os-partner:54563 Change-Id: I56bc6b5292aec676103a436048abee8577edd961 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/15268 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src')
-rw-r--r--src/soc/intel/apollolake/include/soc/spi.h2
-rw-r--r--src/soc/intel/apollolake/spi.c6
2 files changed, 8 insertions, 0 deletions
diff --git a/src/soc/intel/apollolake/include/soc/spi.h b/src/soc/intel/apollolake/include/soc/spi.h
index 1414a84686..f67110f125 100644
--- a/src/soc/intel/apollolake/include/soc/spi.h
+++ b/src/soc/intel/apollolake/include/soc/spi.h
@@ -75,4 +75,6 @@
*/
int spi_read_status(uint8_t *status);
+/* Read SPI controller register. */
+uint32_t spi_ctrlr_reg_read(uint16_t reg);
#endif
diff --git a/src/soc/intel/apollolake/spi.c b/src/soc/intel/apollolake/spi.c
index 879b3a34a9..282ed013a6 100644
--- a/src/soc/intel/apollolake/spi.c
+++ b/src/soc/intel/apollolake/spi.c
@@ -70,6 +70,12 @@ static uint32_t _spi_ctrlr_reg_read(struct spi_ctx *ctx, uint16_t reg)
return read32((void *)addr);
}
+uint32_t spi_ctrlr_reg_read(uint16_t reg)
+{
+ BOILERPLATE_CREATE_CTX(ctx);
+ return _spi_ctrlr_reg_read(ctx, reg);
+}
+
/* Write to register in the SPI controller. 'reg' is the register offset. */
static void _spi_ctrlr_reg_write(struct spi_ctx *ctx, uint16_t reg,
uint32_t val)