diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2021-01-31 00:33:04 +0100 |
|---|---|---|
| committer | Angel Pons <th3fanbus@gmail.com> | 2021-02-07 19:31:34 +0000 |
| commit | c715dc80f92f5cf1d29b53f2b2166e2a4f4b3dc4 (patch) | |
| tree | 08dc25d5ae137d824ae0db2f0be90956f521cbdc /src | |
| parent | 84a37b9d55e8da6137bfeb9d2e866ae4273983a8 (diff) | |
| download | coreboot-c715dc80f92f5cf1d29b53f2b2166e2a4f4b3dc4.tar.xz | |
soc/intel/broadwell: Use common {DMI,EP,MCH}BAR accessors
Tested with BUILD_TIMELESS=1, Purism Librem 13 v1 remains identical.
Change-Id: I04dbeade44d480301c9f7d336449bc54e56cb7bc
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50169
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/intel/broadwell/Kconfig | 9 | ||||
| -rw-r--r-- | src/soc/intel/broadwell/acpi/ctdp.asl | 2 | ||||
| -rw-r--r-- | src/soc/intel/broadwell/acpi/hostbridge.asl | 6 | ||||
| -rw-r--r-- | src/soc/intel/broadwell/early_init.c | 6 | ||||
| -rw-r--r-- | src/soc/intel/broadwell/include/soc/iomap.h | 3 | ||||
| -rw-r--r-- | src/soc/intel/broadwell/include/soc/systemagent.h | 5 |
6 files changed, 17 insertions, 14 deletions
diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig index 4b9af49a5c..1260ae7c40 100644 --- a/src/soc/intel/broadwell/Kconfig +++ b/src/soc/intel/broadwell/Kconfig @@ -86,6 +86,15 @@ config VGA_BIOS_ID string default "8086,0406" +config FIXED_MCHBAR_MMIO_BASE + default 0xfed10000 + +config FIXED_DMIBAR_MMIO_BASE + default 0xfed18000 + +config FIXED_EPBAR_MMIO_BASE + default 0xfed19000 + config DCACHE_RAM_BASE hex default 0xff7c0000 diff --git a/src/soc/intel/broadwell/acpi/ctdp.asl b/src/soc/intel/broadwell/acpi/ctdp.asl index b18ec78ecd..67ceb82ad8 100644 --- a/src/soc/intel/broadwell/acpi/ctdp.asl +++ b/src/soc/intel/broadwell/acpi/ctdp.asl @@ -9,7 +9,7 @@ Scope (\_SB.PCI0.MCHC) Name (CTCU, 2) /* CTDP Up Select */ Name (SPL1, 0) /* Saved PL1 value */ - OperationRegion (MCHB, SystemMemory, MCH_BASE_ADDRESS + 0x5000, 0x1000) + OperationRegion (MCHB, SystemMemory, CONFIG_FIXED_MCHBAR_MMIO_BASE + 0x5000, 0x1000) Field (MCHB, DWordAcc, Lock, Preserve) { Offset (0x930), /* PACKAGE_POWER_SKU */ diff --git a/src/soc/intel/broadwell/acpi/hostbridge.asl b/src/soc/intel/broadwell/acpi/hostbridge.asl index 325a736456..e36fa47677 100644 --- a/src/soc/intel/broadwell/acpi/hostbridge.asl +++ b/src/soc/intel/broadwell/acpi/hostbridge.asl @@ -175,9 +175,9 @@ Device (PDRC) Name (PDRS, ResourceTemplate() { Memory32Fixed (ReadWrite, RCBA_BASE_ADDRESS, RCBA_BASE_SIZE) - Memory32Fixed (ReadWrite, MCH_BASE_ADDRESS, MCH_BASE_SIZE) - Memory32Fixed (ReadWrite, DMI_BASE_ADDRESS, DMI_BASE_SIZE) - Memory32Fixed (ReadWrite, EP_BASE_ADDRESS, EP_BASE_SIZE) + Memory32Fixed (ReadWrite, CONFIG_FIXED_MCHBAR_MMIO_BASE, MCH_BASE_SIZE) + Memory32Fixed (ReadWrite, CONFIG_FIXED_DMIBAR_MMIO_BASE, DMI_BASE_SIZE) + Memory32Fixed (ReadWrite, CONFIG_FIXED_EPBAR_MMIO_BASE, EP_BASE_SIZE) Memory32Fixed (ReadWrite, CONFIG_MMCONF_BASE_ADDRESS, CONFIG_MMCONF_LENGTH) Memory32Fixed (ReadWrite, EDRAM_BASE_ADDRESS, EDRAM_BASE_SIZE) Memory32Fixed (ReadWrite, GDXC_BASE_ADDRESS, GDXC_BASE_SIZE) diff --git a/src/soc/intel/broadwell/early_init.c b/src/soc/intel/broadwell/early_init.c index 6bf7ba7a59..6c347f3380 100644 --- a/src/soc/intel/broadwell/early_init.c +++ b/src/soc/intel/broadwell/early_init.c @@ -11,9 +11,9 @@ static void broadwell_setup_bars(void) { /* Set up all hardcoded northbridge BARs */ - pci_write_config32(SA_DEV_ROOT, MCHBAR, MCH_BASE_ADDRESS | 1); - pci_write_config32(SA_DEV_ROOT, DMIBAR, DMI_BASE_ADDRESS | 1); - pci_write_config32(SA_DEV_ROOT, EPBAR, EP_BASE_ADDRESS | 1); + pci_write_config32(SA_DEV_ROOT, MCHBAR, CONFIG_FIXED_MCHBAR_MMIO_BASE | 1); + pci_write_config32(SA_DEV_ROOT, DMIBAR, CONFIG_FIXED_DMIBAR_MMIO_BASE | 1); + pci_write_config32(SA_DEV_ROOT, EPBAR, CONFIG_FIXED_EPBAR_MMIO_BASE | 1); MCHBAR32(EDRAMBAR) = EDRAM_BASE_ADDRESS | 1; MCHBAR32(GDXCBAR) = GDXC_BASE_ADDRESS | 1; diff --git a/src/soc/intel/broadwell/include/soc/iomap.h b/src/soc/intel/broadwell/include/soc/iomap.h index 8f98fd9266..61e53fc59d 100644 --- a/src/soc/intel/broadwell/include/soc/iomap.h +++ b/src/soc/intel/broadwell/include/soc/iomap.h @@ -3,13 +3,10 @@ #ifndef _BROADWELL_IOMAP_H_ #define _BROADWELL_IOMAP_H_ -#define MCH_BASE_ADDRESS 0xfed10000 #define MCH_BASE_SIZE 0x8000 -#define DMI_BASE_ADDRESS 0xfed18000 #define DMI_BASE_SIZE 0x1000 -#define EP_BASE_ADDRESS 0xfed19000 #define EP_BASE_SIZE 0x1000 #define EDRAM_BASE_ADDRESS 0xfed80000 diff --git a/src/soc/intel/broadwell/include/soc/systemagent.h b/src/soc/intel/broadwell/include/soc/systemagent.h index cc0dc4f0c5..331bbc7ca3 100644 --- a/src/soc/intel/broadwell/include/soc/systemagent.h +++ b/src/soc/intel/broadwell/include/soc/systemagent.h @@ -82,10 +82,7 @@ #define PRSCAPDIS (1 << 2) /* MCHBAR */ - -#define MCHBAR8(x) *((volatile u8 *)(MCH_BASE_ADDRESS + (x))) -#define MCHBAR16(x) *((volatile u16 *)(MCH_BASE_ADDRESS + (x))) -#define MCHBAR32(x) *((volatile u32 *)(MCH_BASE_ADDRESS + (x))) +#include <northbridge/intel/common/fixed_bars.h> /* Memory controller characteristics */ #define NUM_CHANNELS 2 |