diff options
author | Angel Pons <th3fanbus@gmail.com> | 2020-09-14 16:36:28 +0200 |
---|---|---|
committer | Angel Pons <th3fanbus@gmail.com> | 2020-09-17 19:35:19 +0000 |
commit | c8027454baeec2d18c06f537083ca30d3b70c1b0 (patch) | |
tree | 4f8ded82f2026d414c74092f0c85614d68b64ee8 /src | |
parent | 92717ff3e475546366ac6439a4a0d4852bb2cb60 (diff) | |
download | coreboot-c8027454baeec2d18c06f537083ca30d3b70c1b0.tar.xz |
nb/intel/sandybridge: Drop casts from DEFAULT_{MCHBAR,DMIBAR}
This allows us to drop some casts to uintptr_t around the tree.
The MCHBAR32 macro still needs a cast to preserve reproducibility.
Only the native raminit path needs the cast, the MRC path does not.
Tested with BUILD_TIMELESS=1, these boards remain identical:
- Lenovo ThinkPad X230
- Dell OptiPlex 9010
- Roda RW11 (with MRC raminit)
Change-Id: I8ca1c35e2c1f1b4f0d83bd7bb080b8667dbe3cb3
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45349
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
-rw-r--r-- | src/mainboard/asus/p8z77-m_pro/early_init.c | 4 | ||||
-rw-r--r-- | src/mainboard/dell/optiplex_9010/early_init.c | 4 | ||||
-rw-r--r-- | src/mainboard/google/butterfly/early_init.c | 4 | ||||
-rw-r--r-- | src/mainboard/google/link/early_init.c | 4 | ||||
-rw-r--r-- | src/mainboard/google/parrot/early_init.c | 4 | ||||
-rw-r--r-- | src/mainboard/google/stout/early_init.c | 4 | ||||
-rw-r--r-- | src/mainboard/intel/dcp847ske/romstage.c | 4 | ||||
-rw-r--r-- | src/mainboard/intel/emeraldlake2/early_init.c | 4 | ||||
-rw-r--r-- | src/mainboard/kontron/ktqm77/early_init.c | 4 | ||||
-rw-r--r-- | src/mainboard/lenovo/x220/early_init.c | 4 | ||||
-rw-r--r-- | src/mainboard/roda/rv11/variants/rv11/early_init.c | 4 | ||||
-rw-r--r-- | src/mainboard/roda/rv11/variants/rw11/early_init.c | 4 | ||||
-rw-r--r-- | src/mainboard/samsung/lumpy/early_init.c | 4 | ||||
-rw-r--r-- | src/mainboard/samsung/stumpy/early_init.c | 4 | ||||
-rw-r--r-- | src/northbridge/intel/sandybridge/early_init.c | 8 | ||||
-rw-r--r-- | src/northbridge/intel/sandybridge/sandybridge.h | 7 |
16 files changed, 33 insertions, 38 deletions
diff --git a/src/mainboard/asus/p8z77-m_pro/early_init.c b/src/mainboard/asus/p8z77-m_pro/early_init.c index adf23c1df9..81eb6f474c 100644 --- a/src/mainboard/asus/p8z77-m_pro/early_init.c +++ b/src/mainboard/asus/p8z77-m_pro/early_init.c @@ -85,8 +85,8 @@ void mainboard_fill_pei_data(struct pei_data *pei_data) struct pei_data pd = { .pei_version = PEI_VERSION, - .mchbar = (uintptr_t)DEFAULT_MCHBAR, - .dmibar = (uintptr_t)DEFAULT_DMIBAR, + .mchbar = DEFAULT_MCHBAR, + .dmibar = DEFAULT_DMIBAR, .epbar = DEFAULT_EPBAR, .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, .smbusbar = CONFIG_FIXED_SMBUS_IO_BASE, diff --git a/src/mainboard/dell/optiplex_9010/early_init.c b/src/mainboard/dell/optiplex_9010/early_init.c index 5469c94f15..e96ee34aa4 100644 --- a/src/mainboard/dell/optiplex_9010/early_init.c +++ b/src/mainboard/dell/optiplex_9010/early_init.c @@ -32,8 +32,8 @@ void bootblock_mainboard_early_init(void) * FIXME: the board gets stuck in reset loop in * mainboard_romstage_entry. Avoid that by clearing SSKPD */ - pci_write_config32(HOST_BRIDGE, MCHBAR, (uintptr_t)DEFAULT_MCHBAR | 1); - pci_write_config32(HOST_BRIDGE, MCHBAR + 4, (0LL + (uintptr_t)DEFAULT_MCHBAR) >> 32); + pci_write_config32(HOST_BRIDGE, MCHBAR, DEFAULT_MCHBAR | 1); + pci_write_config32(HOST_BRIDGE, MCHBAR + 4, (0LL + DEFAULT_MCHBAR) >> 32); MCHBAR16(SSKPD_HI) = 0; sch5545_early_init(0x2e); diff --git a/src/mainboard/google/butterfly/early_init.c b/src/mainboard/google/butterfly/early_init.c index ce585b042d..2ffa3aa5e9 100644 --- a/src/mainboard/google/butterfly/early_init.c +++ b/src/mainboard/google/butterfly/early_init.c @@ -79,8 +79,8 @@ void mainboard_fill_pei_data(struct pei_data *pei_data) { struct pei_data pei_data_template = { .pei_version = PEI_VERSION, - .mchbar = (uintptr_t)DEFAULT_MCHBAR, - .dmibar = (uintptr_t)DEFAULT_DMIBAR, + .mchbar = DEFAULT_MCHBAR, + .dmibar = DEFAULT_DMIBAR, .epbar = DEFAULT_EPBAR, .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, .smbusbar = CONFIG_FIXED_SMBUS_IO_BASE, diff --git a/src/mainboard/google/link/early_init.c b/src/mainboard/google/link/early_init.c index 312d64a816..f3da77cd6b 100644 --- a/src/mainboard/google/link/early_init.c +++ b/src/mainboard/google/link/early_init.c @@ -86,8 +86,8 @@ void mainboard_fill_pei_data(struct pei_data *pei_data) { struct pei_data pei_data_template = { .pei_version = PEI_VERSION, - .mchbar = (uintptr_t)DEFAULT_MCHBAR, - .dmibar = (uintptr_t)DEFAULT_DMIBAR, + .mchbar = DEFAULT_MCHBAR, + .dmibar = DEFAULT_DMIBAR, .epbar = DEFAULT_EPBAR, .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, .smbusbar = CONFIG_FIXED_SMBUS_IO_BASE, diff --git a/src/mainboard/google/parrot/early_init.c b/src/mainboard/google/parrot/early_init.c index 1883ae8732..f0ffc9fe4c 100644 --- a/src/mainboard/google/parrot/early_init.c +++ b/src/mainboard/google/parrot/early_init.c @@ -54,8 +54,8 @@ void mainboard_fill_pei_data(struct pei_data *pei_data) { struct pei_data pei_data_template = { .pei_version = PEI_VERSION, - .mchbar = (uintptr_t)DEFAULT_MCHBAR, - .dmibar = (uintptr_t)DEFAULT_DMIBAR, + .mchbar = DEFAULT_MCHBAR, + .dmibar = DEFAULT_DMIBAR, .epbar = DEFAULT_EPBAR, .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, .smbusbar = CONFIG_FIXED_SMBUS_IO_BASE, diff --git a/src/mainboard/google/stout/early_init.c b/src/mainboard/google/stout/early_init.c index 7bd101239c..f2f21bc0d2 100644 --- a/src/mainboard/google/stout/early_init.c +++ b/src/mainboard/google/stout/early_init.c @@ -91,8 +91,8 @@ void mainboard_fill_pei_data(struct pei_data *pei_data) { struct pei_data pei_data_template = { .pei_version = PEI_VERSION, - .mchbar = (uintptr_t)DEFAULT_MCHBAR, - .dmibar = (uintptr_t)DEFAULT_DMIBAR, + .mchbar = DEFAULT_MCHBAR, + .dmibar = DEFAULT_DMIBAR, .epbar = DEFAULT_EPBAR, .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, .smbusbar = CONFIG_FIXED_SMBUS_IO_BASE, diff --git a/src/mainboard/intel/dcp847ske/romstage.c b/src/mainboard/intel/dcp847ske/romstage.c index d793aca891..391d1f23b2 100644 --- a/src/mainboard/intel/dcp847ske/romstage.c +++ b/src/mainboard/intel/dcp847ske/romstage.c @@ -14,8 +14,8 @@ void mainboard_fill_pei_data(struct pei_data *pei_data) { struct pei_data pei_data_template = { .pei_version = PEI_VERSION, - .mchbar = (uintptr_t)DEFAULT_MCHBAR, - .dmibar = (uintptr_t)DEFAULT_DMIBAR, + .mchbar = DEFAULT_MCHBAR, + .dmibar = DEFAULT_DMIBAR, .epbar = DEFAULT_EPBAR, .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, .smbusbar = CONFIG_FIXED_SMBUS_IO_BASE, diff --git a/src/mainboard/intel/emeraldlake2/early_init.c b/src/mainboard/intel/emeraldlake2/early_init.c index 1d068c3308..a2aaf33bb0 100644 --- a/src/mainboard/intel/emeraldlake2/early_init.c +++ b/src/mainboard/intel/emeraldlake2/early_init.c @@ -51,8 +51,8 @@ void mainboard_fill_pei_data(struct pei_data *pei_data) { struct pei_data pei_data_template = { .pei_version = PEI_VERSION, - .mchbar = (uintptr_t)DEFAULT_MCHBAR, - .dmibar = (uintptr_t)DEFAULT_DMIBAR, + .mchbar = DEFAULT_MCHBAR, + .dmibar = DEFAULT_DMIBAR, .epbar = DEFAULT_EPBAR, .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, .smbusbar = CONFIG_FIXED_SMBUS_IO_BASE, diff --git a/src/mainboard/kontron/ktqm77/early_init.c b/src/mainboard/kontron/ktqm77/early_init.c index a45c24da95..d1aa9d5dc8 100644 --- a/src/mainboard/kontron/ktqm77/early_init.c +++ b/src/mainboard/kontron/ktqm77/early_init.c @@ -56,8 +56,8 @@ void mainboard_fill_pei_data(struct pei_data *pei_data) { struct pei_data pei_data_template = { .pei_version = PEI_VERSION, - .mchbar = (uintptr_t)DEFAULT_MCHBAR, - .dmibar = (uintptr_t)DEFAULT_DMIBAR, + .mchbar = DEFAULT_MCHBAR, + .dmibar = DEFAULT_DMIBAR, .epbar = DEFAULT_EPBAR, .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, .smbusbar = CONFIG_FIXED_SMBUS_IO_BASE, diff --git a/src/mainboard/lenovo/x220/early_init.c b/src/mainboard/lenovo/x220/early_init.c index 109f08be6a..bb120bfa0e 100644 --- a/src/mainboard/lenovo/x220/early_init.c +++ b/src/mainboard/lenovo/x220/early_init.c @@ -12,8 +12,8 @@ void mainboard_fill_pei_data(struct pei_data *pei_data) { struct pei_data pei_data_template = { .pei_version = PEI_VERSION, - .mchbar = (uintptr_t)DEFAULT_MCHBAR, - .dmibar = (uintptr_t)DEFAULT_DMIBAR, + .mchbar = DEFAULT_MCHBAR, + .dmibar = DEFAULT_DMIBAR, .epbar = DEFAULT_EPBAR, .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, .smbusbar = CONFIG_FIXED_SMBUS_IO_BASE, diff --git a/src/mainboard/roda/rv11/variants/rv11/early_init.c b/src/mainboard/roda/rv11/variants/rv11/early_init.c index 410fc63037..5b55873eb1 100644 --- a/src/mainboard/roda/rv11/variants/rv11/early_init.c +++ b/src/mainboard/roda/rv11/variants/rv11/early_init.c @@ -10,8 +10,8 @@ void mainboard_fill_pei_data(struct pei_data *const pei_data) { const struct pei_data pei_data_template = { .pei_version = PEI_VERSION, - .mchbar = (uintptr_t)DEFAULT_MCHBAR, - .dmibar = (uintptr_t)DEFAULT_DMIBAR, + .mchbar = DEFAULT_MCHBAR, + .dmibar = DEFAULT_DMIBAR, .epbar = DEFAULT_EPBAR, .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, .smbusbar = CONFIG_FIXED_SMBUS_IO_BASE, diff --git a/src/mainboard/roda/rv11/variants/rw11/early_init.c b/src/mainboard/roda/rv11/variants/rw11/early_init.c index 38521bec93..7076eb7358 100644 --- a/src/mainboard/roda/rv11/variants/rw11/early_init.c +++ b/src/mainboard/roda/rv11/variants/rw11/early_init.c @@ -40,8 +40,8 @@ void mainboard_fill_pei_data(struct pei_data *const pei_data) { const struct pei_data pei_data_template = { .pei_version = PEI_VERSION, - .mchbar = (uintptr_t)DEFAULT_MCHBAR, - .dmibar = (uintptr_t)DEFAULT_DMIBAR, + .mchbar = DEFAULT_MCHBAR, + .dmibar = DEFAULT_DMIBAR, .epbar = DEFAULT_EPBAR, .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, .smbusbar = CONFIG_FIXED_SMBUS_IO_BASE, diff --git a/src/mainboard/samsung/lumpy/early_init.c b/src/mainboard/samsung/lumpy/early_init.c index e90228cc18..ad4ddb91ee 100644 --- a/src/mainboard/samsung/lumpy/early_init.c +++ b/src/mainboard/samsung/lumpy/early_init.c @@ -117,8 +117,8 @@ void mainboard_fill_pei_data(struct pei_data *pei_data) { struct pei_data pei_data_template = { .pei_version = PEI_VERSION, - .mchbar = (uintptr_t)DEFAULT_MCHBAR, - .dmibar = (uintptr_t)DEFAULT_DMIBAR, + .mchbar = DEFAULT_MCHBAR, + .dmibar = DEFAULT_DMIBAR, .epbar = DEFAULT_EPBAR, .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, .smbusbar = CONFIG_FIXED_SMBUS_IO_BASE, diff --git a/src/mainboard/samsung/stumpy/early_init.c b/src/mainboard/samsung/stumpy/early_init.c index 09b23d691c..7d4a9a4411 100644 --- a/src/mainboard/samsung/stumpy/early_init.c +++ b/src/mainboard/samsung/stumpy/early_init.c @@ -101,8 +101,8 @@ void mainboard_fill_pei_data(struct pei_data *pei_data) { struct pei_data pei_data_template = { .pei_version = PEI_VERSION, - .mchbar = (uintptr_t)DEFAULT_MCHBAR, - .dmibar = (uintptr_t)DEFAULT_DMIBAR, + .mchbar = DEFAULT_MCHBAR, + .dmibar = DEFAULT_DMIBAR, .epbar = DEFAULT_EPBAR, .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, .smbusbar = CONFIG_FIXED_SMBUS_IO_BASE, diff --git a/src/northbridge/intel/sandybridge/early_init.c b/src/northbridge/intel/sandybridge/early_init.c index 2ee273c1f4..45b5b8f10a 100644 --- a/src/northbridge/intel/sandybridge/early_init.c +++ b/src/northbridge/intel/sandybridge/early_init.c @@ -52,10 +52,10 @@ static void sandybridge_setup_bars(void) /* Set up all hardcoded northbridge BARs */ pci_write_config32(HOST_BRIDGE, EPBAR, DEFAULT_EPBAR | 1); pci_write_config32(HOST_BRIDGE, EPBAR + 4, (0LL + DEFAULT_EPBAR) >> 32); - pci_write_config32(HOST_BRIDGE, MCHBAR, (uintptr_t)DEFAULT_MCHBAR | 1); - pci_write_config32(HOST_BRIDGE, MCHBAR + 4, (0LL + (uintptr_t)DEFAULT_MCHBAR) >> 32); - pci_write_config32(HOST_BRIDGE, DMIBAR, (uintptr_t)DEFAULT_DMIBAR | 1); - pci_write_config32(HOST_BRIDGE, DMIBAR + 4, (0LL + (uintptr_t)DEFAULT_DMIBAR) >> 32); + pci_write_config32(HOST_BRIDGE, MCHBAR, DEFAULT_MCHBAR | 1); + pci_write_config32(HOST_BRIDGE, MCHBAR + 4, (0LL + DEFAULT_MCHBAR) >> 32); + pci_write_config32(HOST_BRIDGE, DMIBAR, DEFAULT_DMIBAR | 1); + pci_write_config32(HOST_BRIDGE, DMIBAR + 4, (0LL + DEFAULT_DMIBAR) >> 32); printk(BIOS_DEBUG, " done\n"); } diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h index 94a8e6f4aa..cfc37c864b 100644 --- a/src/northbridge/intel/sandybridge/sandybridge.h +++ b/src/northbridge/intel/sandybridge/sandybridge.h @@ -21,13 +21,8 @@ #define IVB_STEP_D0 (BASE_REV_IVB + 6) /* Northbridge BARs */ -#ifndef __ACPI__ -#define DEFAULT_MCHBAR ((u8 *)0xfed10000) /* 16 KB */ -#define DEFAULT_DMIBAR ((u8 *)0xfed18000) /* 4 KB */ -#else #define DEFAULT_MCHBAR 0xfed10000 /* 16 KB */ #define DEFAULT_DMIBAR 0xfed18000 /* 4 KB */ -#endif #define DEFAULT_EPBAR 0xfed19000 /* 4 KB */ #define GFXVT_BASE 0xfed90000ULL @@ -65,7 +60,7 @@ enum platform_type { #define MCHBAR8(x) (*((volatile u8 *)(DEFAULT_MCHBAR + (x)))) #define MCHBAR16(x) (*((volatile u16 *)(DEFAULT_MCHBAR + (x)))) -#define MCHBAR32(x) (*((volatile u32 *)(DEFAULT_MCHBAR + (x)))) +#define MCHBAR32(x) (*((volatile u32 *)((void *)DEFAULT_MCHBAR + (x)))) #define MCHBAR8_AND(x, and) (MCHBAR8(x) = MCHBAR8(x) & (and)) #define MCHBAR16_AND(x, and) (MCHBAR16(x) = MCHBAR16(x) & (and)) #define MCHBAR32_AND(x, and) (MCHBAR32(x) = MCHBAR32(x) & (and)) |