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| author | Angel Pons <th3fanbus@gmail.com> | 2020-10-28 23:53:45 +0100 |
|---|---|---|
| committer | Angel Pons <th3fanbus@gmail.com> | 2021-01-24 12:00:59 +0000 |
| commit | c86b11949506637c281011a0e246e5ae07a9a13b (patch) | |
| tree | a491afd1d6b8c41565330b26c94fe00d11c1ecfa /src | |
| parent | 8b043c058cd58da46db268a9d61b80fd893cf90d (diff) | |
| download | coreboot-c86b11949506637c281011a0e246e5ae07a9a13b.tar.xz | |
cpu/intel/haswell: Add fast ramp voltage for Broadwell
Backport commit 55228ba4b4 (broadwell: Changes from 2.2.0 ref code) to
Haswell, to eventually migrate Broadwell to use the same Haswell code.
Change-Id: I03d9ff16bcaab9091bd723ce933aa3f2d71e29b9
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46921
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/cpu/intel/haswell/haswell.h | 6 | ||||
| -rw-r--r-- | src/cpu/intel/haswell/haswell_init.c | 7 |
2 files changed, 11 insertions, 2 deletions
diff --git a/src/cpu/intel/haswell/haswell.h b/src/cpu/intel/haswell/haswell.h index cb602ceaa9..e45acd5a27 100644 --- a/src/cpu/intel/haswell/haswell.h +++ b/src/cpu/intel/haswell/haswell.h @@ -3,6 +3,7 @@ #ifndef _CPU_INTEL_HASWELL_H #define _CPU_INTEL_HASWELL_H +#include <arch/cpu.h> #include <stdint.h> /* CPU types without stepping */ @@ -168,6 +169,11 @@ void set_power_limits(u8 power_limit_1_time); int cpu_config_tdp_levels(void); /* CPU identification */ +static inline u32 cpu_family_model(void) +{ + return cpuid_eax(1) & 0x0fff0ff0; +} + static inline int haswell_is_ult(void) { return CONFIG(INTEL_LYNXPOINT_LP); diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c index 9881bb880f..b1f8bba815 100644 --- a/src/cpu/intel/haswell/haswell_init.c +++ b/src/cpu/intel/haswell/haswell_init.c @@ -294,8 +294,11 @@ static void initialize_vr_config(void) msr = rdmsr(MSR_VR_MISC_CONFIG2); msr.lo &= ~0xffff; /* Allow CPU to control minimum voltage completely (15:8) and - * set the fast ramp voltage to 1110mV (0x6f in 10mV steps). */ - msr.lo |= 0x006f; + set the fast ramp voltage in 10mV steps. */ + if (cpu_family_model() == BROADWELL_FAMILY_ULT) + msr.lo |= 0x006a; /* 1.56V */ + else + msr.lo |= 0x006f; /* 1.60V */ wrmsr(MSR_VR_MISC_CONFIG2, msr); } |