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authorSubrata Banik <subrata.banik@intel.com>2021-03-22 15:50:08 +0530
committerSubrata Banik <subrata.banik@intel.com>2021-03-26 04:52:57 +0000
commitc8ac8f5ce969196f9e38e24629120ab8c5a4c873 (patch)
treeb05c98e9ea1c3bfac49e92de86faf44544598cd9 /src
parent74406e10539336e6eb201e56c4ee559c54973f03 (diff)
downloadcoreboot-c8ac8f5ce969196f9e38e24629120ab8c5a4c873.tar.xz
soc/intel/alderlake: Align RcompResistor definition as per MRC
List of changes: 1. Alder Lake MRC is expecting a RcompResistor value of word width. Reference RCOMP resistors on motherboard are ~ 100 Ohms but coreboot is passing an array of RcompResistor which is not completely in use. Note: Rcomp resistor value represents rcomp resistor attached to the DDR_COMP pins on the SoC. 2. Also, remove usage of '&' with memcpy the required value into RcompTarget array. 3. Also, update RcompResistor value for ADLRVP. BUG=b:183341229 TEST=Enable FSP debug log to verify the override value for RcompResistor is reflecting correctly. Change-Id: I69c7cec55b65036fc039c33374a3fd363ef7004e Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51704 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src')
-rw-r--r--src/mainboard/intel/adlrvp/memory.c8
-rw-r--r--src/soc/intel/alderlake/include/soc/meminit.h7
-rw-r--r--src/soc/intel/alderlake/meminit.c5
3 files changed, 9 insertions, 11 deletions
diff --git a/src/mainboard/intel/adlrvp/memory.c b/src/mainboard/intel/adlrvp/memory.c
index 6f158a057f..68f7fca483 100644
--- a/src/mainboard/intel/adlrvp/memory.c
+++ b/src/mainboard/intel/adlrvp/memory.c
@@ -14,8 +14,8 @@ static const struct mb_cfg ddr4_mem_config = {
.ddr_config = {
- /* Baseboard uses only 100ohm Rcomp resistors */
- .rcomp_resistor = {100, 100, 100},
+ /* Baseboard uses only 100ohm Rcomp resistor */
+ .rcomp_resistor = 100,
/* Baseboard Rcomp target values */
.rcomp_targets = {40, 30, 33, 33, 30},
@@ -148,8 +148,8 @@ static const struct mb_cfg ddr5_mem_config = {
.UserBd = BOARD_TYPE_MOBILE,
.ddr_config = {
- /* Baseboard uses only 100ohm Rcomp resistors */
- .rcomp_resistor = {100, 100, 100},
+ /* Baseboard uses only 100ohm Rcomp resistor */
+ .rcomp_resistor = 100,
/* Baseboard Rcomp target values */
.rcomp_targets = {50, 30, 30, 30, 27},
diff --git a/src/soc/intel/alderlake/include/soc/meminit.h b/src/soc/intel/alderlake/include/soc/meminit.h
index ae86cc6da4..9813d9345e 100644
--- a/src/soc/intel/alderlake/include/soc/meminit.h
+++ b/src/soc/intel/alderlake/include/soc/meminit.h
@@ -20,11 +20,10 @@ struct mem_ddr_config {
/* Dqs Pins Interleaved Setting. Enable/Disable Control */
bool dq_pins_interleaved;
/*
- * Rcomp resistor values. These values represent the resistance in
- * ohms of the three rcomp resistors attached to the DDR_COMP_0,
- * DDR_COMP_1, and DDR_COMP_2 pins on the DRAM.
+ * Rcomp resistor value. This values represents the resistance in
+ * ohms of the rcomp resistor attached to the DDR_COMP pin on the SoC.
*/
- uint16_t rcomp_resistor[3];
+ uint16_t rcomp_resistor;
/* Rcomp target values. */
uint16_t rcomp_targets[5];
};
diff --git a/src/soc/intel/alderlake/meminit.c b/src/soc/intel/alderlake/meminit.c
index 5b65ef063f..dcff61113a 100644
--- a/src/soc/intel/alderlake/meminit.c
+++ b/src/soc/intel/alderlake/meminit.c
@@ -28,9 +28,8 @@ static void meminit_lp5x(FSP_M_CONFIG *mem_cfg, const struct mem_lp5x_config *lp
static void meminit_ddr(FSP_M_CONFIG *mem_cfg, const struct mem_ddr_config *ddr_config)
{
mem_cfg->DqPinsInterleaved = ddr_config->dq_pins_interleaved;
- memcpy(&mem_cfg->RcompResistor, ddr_config->rcomp_resistor,
- sizeof(mem_cfg->RcompResistor));
- memcpy(&mem_cfg->RcompTarget, ddr_config->rcomp_targets, sizeof(mem_cfg->RcompTarget));
+ mem_cfg->RcompResistor = ddr_config->rcomp_resistor;
+ memcpy(mem_cfg->RcompTarget, ddr_config->rcomp_targets, sizeof(mem_cfg->RcompTarget));
}
static const struct soc_mem_cfg soc_mem_cfg[] = {