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| author | Angel Pons <th3fanbus@gmail.com> | 2020-06-21 17:58:59 +0200 |
|---|---|---|
| committer | Angel Pons <th3fanbus@gmail.com> | 2020-06-27 17:29:02 +0000 |
| commit | c9ee2c0323e0e9fb2094651eac383898057cc2ab (patch) | |
| tree | cbb3d78cb2cfc94b6ae3651a9d4f5f24aa8b10f8 /src | |
| parent | fc7bc54e34d496a9fe2d0047eddeb9d1f48de417 (diff) | |
| download | coreboot-c9ee2c0323e0e9fb2094651eac383898057cc2ab.tar.xz | |
sb/intel/bd82x6x: Use common early SPI code
Change-Id: If4843e93c993ed2de60b2b6064c2c9e98637ce9a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42661
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/southbridge/intel/bd82x6x/bootblock.c | 11 |
1 files changed, 2 insertions, 9 deletions
diff --git a/src/southbridge/intel/bd82x6x/bootblock.c b/src/southbridge/intel/bd82x6x/bootblock.c index 3a99f512c6..a3228e7e52 100644 --- a/src/southbridge/intel/bd82x6x/bootblock.c +++ b/src/southbridge/intel/bd82x6x/bootblock.c @@ -2,16 +2,9 @@ #include <arch/bootblock.h> #include <device/pci_ops.h> +#include <southbridge/intel/common/early_spi.h> #include "pch.h" -/* - * Enable Prefetching and Caching. - */ -static void enable_spi_prefetch(void) -{ - pci_update_config8(PCH_LPC_DEV, BIOS_CNTL, ~(3 << 2), 2 << 2); -} - static void enable_port80_on_lpc(void) { /* Enable port 80 POST on LPC */ @@ -40,7 +33,7 @@ static void set_spi_speed(void) void bootblock_early_southbridge_init(void) { - enable_spi_prefetch(); + enable_spi_prefetching_and_caching(); early_pch_init(); |