diff options
| author | Michael Niewöhner <foss@mniewoehner.de> | 2019-10-26 10:44:33 +0200 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2019-11-02 16:13:24 +0000 |
| commit | d60089b7b1f32271da109997c53f85dab6c03afd (patch) | |
| tree | 7201e7cc8ac5ea611ef9e3fb4f693b5ccaf8ade0 /src | |
| parent | de09679c13954e81697ecfd469b438b4d27a81b6 (diff) | |
| download | coreboot-d60089b7b1f32271da109997c53f85dab6c03afd.tar.xz | |
soc/intel/skylake: set FSP param to enable or skip GOP
Set the FSP parameter PeiGraphicsPeimInit according to RUN_FSP_GOP to
enable or skip GOP.
Change-Id: I5731003c8a094c4d108efbea14d31d335758bbb7
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36350
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/intel/skylake/chip.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c index c4f4e50cd2..7987f46954 100644 --- a/src/soc/intel/skylake/chip.c +++ b/src/soc/intel/skylake/chip.c @@ -509,6 +509,12 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) params->PchIoApicFunctionNumber = V_P2SB_IBDF_FUN; } + dev = pcidev_path_on_root(SA_DEVFN_IGD); + if (CONFIG(RUN_FSP_GOP) && dev && dev->enabled) + params->PeiGraphicsPeimInit = 1; + else + params->PeiGraphicsPeimInit = 0; + soc_irq_settings(params); } |