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authorDuncan Laurie <dlaurie@chromium.org>2013-09-25 14:05:31 -0700
committerPatrick Georgi <patrick@georgi-clan.de>2014-08-10 22:19:58 +0200
commitd988b612c76cb34f689c567e9e983e496f65008a (patch)
tree01acfa79c920b335167f8dee9c4e2fcf1f21f3dd /src
parentcff6667eba803498e2f93af68e6e2edbba2353e5 (diff)
downloadcoreboot-d988b612c76cb34f689c567e9e983e496f65008a.tar.xz
bolt: Set GPIO29 as input in S0, output+high in S3/S5
This resolves WiFi issues after suspend/resume. It needs related SPI descriptor soft strap change to enable SLP_WLAN as a GPIO instead of owned by the ME. Change-Id: I03f4458d1e52a913770d391061baa6cfa41e8558 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/170577 Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit cf1fe0524ad4793c8c422dc3fed3007b7fc96038) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6533 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Diffstat (limited to 'src')
-rw-r--r--src/mainboard/google/bolt/gpio.h2
-rw-r--r--src/mainboard/google/bolt/smihandler.c24
2 files changed, 25 insertions, 1 deletions
diff --git a/src/mainboard/google/bolt/gpio.h b/src/mainboard/google/bolt/gpio.h
index 4e7e8c4499..ff6069c7e1 100644
--- a/src/mainboard/google/bolt/gpio.h
+++ b/src/mainboard/google/bolt/gpio.h
@@ -52,7 +52,7 @@ const struct pch_lp_gpio_map mainboard_gpio_map[] = {
LP_GPIO_UNUSED, /* 26: UNUSED */
LP_GPIO_UNUSED, /* 27: UNUSED */
LP_GPIO_UNUSED, /* 28: UNUSED */
- LP_GPIO_NATIVE, /* 29: NATIVE: WLAN_OFF_L */
+ LP_GPIO_INPUT, /* 29: NATIVE: WLAN_OFF_L */
LP_GPIO_NATIVE, /* 30: NATIVE: PCH_SUSWARN_L */
LP_GPIO_NATIVE, /* 31: NATIVE: ACOK_BUF */
LP_GPIO_NATIVE, /* 32: NATIVE: LPC_CLKRUN_L */
diff --git a/src/mainboard/google/bolt/smihandler.c b/src/mainboard/google/bolt/smihandler.c
index b3928524fd..54dcb73077 100644
--- a/src/mainboard/google/bolt/smihandler.c
+++ b/src/mainboard/google/bolt/smihandler.c
@@ -21,6 +21,7 @@
#include <arch/io.h>
#include <console/console.h>
#include <cpu/x86/smm.h>
+#include <southbridge/intel/lynxpoint/lp_gpio.h>
#include <southbridge/intel/lynxpoint/nvs.h>
#include <southbridge/intel/lynxpoint/pch.h>
#include <southbridge/intel/lynxpoint/me.h>
@@ -87,6 +88,26 @@ void mainboard_smi_gpi(u32 gpi_sts)
}
}
+static void bolt_wlan_off(void)
+{
+ u16 gpio_base = pci_read_config16(PCH_LPC_DEV, GPIO_BASE) & 0xfffc;
+ u32 gpio_conf;
+
+ /* Make sure pin is owned by GPIO subsystem and not ACPI */
+ gpio_conf = inl(gpio_base + GPIO_OWNER(0));
+ gpio_conf |= GPIO_OWNER_GPIO << 29;
+ outl(gpio_conf, gpio_base + GPIO_OWNER(0));
+
+ /* Set GPIO29 config to only be reset on RSMRST */
+ gpio_conf = inl(gpio_base + GPIO_RESET(0));
+ gpio_conf |= GPIO_RESET_RSMRST << 29;
+ outl(gpio_conf, gpio_base + GPIO_RESET(0));
+
+ /* Set WLAN_OFF_L (GPIO29) as Output GPIO driven high */
+ gpio_conf = GPIO_MODE_GPIO | GPIO_DIR_OUTPUT | GPO_LEVEL_HIGH;
+ outl(gpio_conf, gpio_base + GPIO_CONFIG0(29));
+}
+
void mainboard_smi_sleep(u8 slp_typ)
{
/* Disable USB charging if required */
@@ -109,6 +130,9 @@ void mainboard_smi_sleep(u8 slp_typ)
break;
}
+ /* Set WLAN_OFF GPIO state */
+ bolt_wlan_off();
+
/* Disable SCI and SMI events */
google_chromeec_set_smi_mask(0);
google_chromeec_set_sci_mask(0);