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authorRonald G. Minnich <rminnich@gmail.com>2006-07-21 19:21:38 +0000
committerRonald G. Minnich <rminnich@gmail.com>2006-07-21 19:21:38 +0000
commitda7ee9fa07b4eaebd6e16faa678d814d9ba03ef1 (patch)
treec86847785bdcd547d0121314f6021c4dc5482f26 /src
parent35befb75ead1b4bc34ef351bec2a411a3ee70519 (diff)
downloadcoreboot-da7ee9fa07b4eaebd6e16faa678d814d9ba03ef1.tar.xz
These changes incorporate steve goodrich'es fixes, and one bug that is
disabled. cs5536: add new entires for SB control etc. cs5536.c: chip_enabled function moved to chip_init, so it only gets run once. IRQ setup improved gx2def.h: new defines added vr.h: new file, with new def's for virtual register control. mainboard config.lb: new entries added for nb and sb control. chipsetinit.c: new controls added -- I forget all the details :-) grphinit.c: new function added northbridge.c: new IRQ control added. FlashChipSetup added, controlled by chip info setupflash struct member. Currently, if enabled, this hangs OLPC in linux PCI scan. chip.h: new struct members added for unwanted device enable, flash setup git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2345 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src')
-rw-r--r--src/include/cpu/amd/gx2def.h30
-rw-r--r--src/include/cpu/amd/vr.h486
-rw-r--r--src/mainboard/olpc/rev_a/Config.lb6
-rw-r--r--src/northbridge/amd/gx2/chip.h3
-rw-r--r--src/northbridge/amd/gx2/chipsetinit.c90
-rw-r--r--src/northbridge/amd/gx2/grphinit.c24
-rw-r--r--src/northbridge/amd/gx2/northbridge.c65
-rw-r--r--src/southbridge/amd/cs5536/chip.h4
-rw-r--r--src/southbridge/amd/cs5536/cs5536.c67
9 files changed, 709 insertions, 66 deletions
diff --git a/src/include/cpu/amd/gx2def.h b/src/include/cpu/amd/gx2def.h
index fd466afe48..8e64659120 100644
--- a/src/include/cpu/amd/gx2def.h
+++ b/src/include/cpu/amd/gx2def.h
@@ -1097,4 +1097,34 @@
#define PM_AWKD ( PMLogic_BASE + 0x50)
#define PM_SSC ( PMLogic_BASE + 0x54)
+
+/* FLASH device macros */
+#define FLASH_TYPE_NONE 0 /* No flash device installed */
+#define FLASH_TYPE_NAND 1 /* NAND device */
+#define FLASH_TYPE_NOR 2 /* NOR device */
+
+#define FLASH_IF_MEM 1 /* Memory or memory-mapped I/O interface for Flash device */
+#define FLASH_IF_IO 2 /* I/O interface for Flash device */
+
+/* Flash Memory Mask values */
+#define FLASH_MEM_DEFAULT 0x00000000
+#define FLASH_MEM_4K 0xFFFFF000
+#define FLASH_MEM_8K 0xFFFFE000
+#define FLASH_MEM_16K 0xFFFFC000
+#define FLASH_MEM_128K 0xFFFE0000
+#define FLASH_MEM_512K 0xFFFC0000
+#define FLASH_MEM_4M 0xFFC00000
+#define FLASH_MEM_8M 0xFF800000
+#define FLASH_MEM_16M 0xFF000000
+
+/* Flash IO Mask values */
+#define FLASH_IO_DEFAULT 0x00000000
+#define FLASH_IO_16B 0x0000FFF0
+#define FLASH_IO_32B 0x0000FFE0
+#define FLASH_IO_64B 0x0000FFC0
+#define FLASH_IO_128B 0x0000FF80
+#define FLASH_IO_256B 0x0000FF00
+
+
+
#endif /* CPU_AMD_GX2DEF_H */
diff --git a/src/include/cpu/amd/vr.h b/src/include/cpu/amd/vr.h
new file mode 100644
index 0000000000..0626545336
--- /dev/null
+++ b/src/include/cpu/amd/vr.h
@@ -0,0 +1,486 @@
+/* <LIC_AMD_STD>
+ * Copyright (C) 2003-2005 Advanced Micro Devices, Inc. All Rights Reserved.
+ * </LIC_AMD_STD> */
+//<CTL_AMD_STD>
+//$Id: //bios/main/vsa_ii/inc/vr.h#18 $
+//$Header: //bios/main/vsa_ii/inc/vr.h#18 $
+//$Date: 2005/09/29 $
+//$DateTime: 2005/09/29 11:07:14 $
+//$Change: 65425 $
+//$File: //bios/main/vsa_ii/inc/vr.h $
+//$Revision: #18 $
+//$Author: johnk $
+//</CTL_AMD_STD>
+//<DOC_AMD_STD>
+// Virtual Register USAGE:
+//
+// Index: AH = Class, AL = Parameter_ID
+// Data: AX = data
+//</DOC_AMD_STD>
+
+#define VRC_INDEX 0xAC1C // Index register
+#define VRC_DATA 0xAC1E // Data register
+#define VR_UNLOCK 0xFC53 // Virtual register unlock code
+#define NO_VR -1 // No virtual registers
+
+#define VRC_MISCELLANEOUS 0x00 // Miscellaneous Class
+ #define VSA_VERSION_NUM 0x00
+ #define HIGH_MEM_ACCESS 0x01
+ #define GET_VSM_INFO 0x02 // Used by INFO
+ #define GET_BASICS 0x00
+ #define GET_EVENT 0x01
+ #define GET_STATISTICS 0x02
+ #define GET_HISTORY 0x03
+ #define GET_HARDWARE 0x04
+ #define GET_ERROR 0x05
+ #define SET_VSM_TYPE 0x06
+ #define SIGNATURE 0x03
+ #define VSA2_SIGNATURE 0x56534132 // 'VSA2' returned in EAX
+
+ #define GET_HW_INFO 0x04
+ #define VSM_VERSION 0x05
+ #define CTRL_ALT_DEL 0x06
+ #define MSR_ACCESS 0x07
+ #define GET_DESCR_INFO 0x08
+ #define PCI_INT_AB 0x09 // GPIO pins for INTA# and INTB#
+ #define PCI_INT_CD 0x0A // GPIO pins for INTC# and INTD#
+ #define WATCHDOG 0x0B // Watchdog timer
+
+ #define MAX_MISC WATCHDOG
+
+
+// NOTE: Do not change the order of the following registers:
+#define VRC_AUDIO 0x01 // XpressAudio Class
+ #define AUDIO_VERSION 0x00
+ #define PM_STATE 0x01
+ #define SB_16_IO_BASE 0x02
+ #define MIDI_BASE 0x03
+ #define CPU_USAGE 0x04
+ #define CODEC_TYPE 0x05
+ #define STATE_INDEX 0x06
+ #define STATE_DATA 0x07
+ #define AUDIO_IRQ 0x08 // For use by native audio drivers
+ #define STATUS_PTR 0x09 // For use by native audio drivers
+ #define MAX_AUDIO STATUS_PTR
+
+#define VRC_VG 0x02 // SoftVG Class
+#define VRC_VGA 0x02 // SoftVGA Class
+ #define VG_MEM_SIZE 0x00 // bits 7:0 - 512K unit size, bit 8 controller priority
+ #define VG_CONFIG 0x00 // Main configuration register
+ #define VG_CFG_BYPASS 0x0001 // DOTPLL bypass bit
+ #define VG_MEM_MASK 0x00FE // Memory size mask bits, 2MB increment
+ #define VG_CFG_DSMASK 0x0700 // Active display mask bits
+ #define VG_CFG_DSCRT 0x0000 // Active display is CRT
+ #define VG_CFG_DSPAN 0x0100 // Active display is panel
+ #define VG_CFG_DSTV 0x0200 // Active display is TV
+ #define VG_CFG_DSSIM 0x0400 // Simultaneous CRT
+ #define VG_CFG_PRIORITY 0x0800 // Controller priority bit
+ #define VG_CFG_MONO 0x1000 // External monochrome card support bit
+ #define VG_CFG_DRIVER 0x2000 // Driver active bit
+ #define VG_CRTC_DIAG 0x8000 // Enable CRTC emulation
+
+ // Defined for GX3/GX3VG
+ #define VG_REFRESH 0x01 // Mode refresh, a mode switch without changing modes
+ #define VG_FRSH_REF_MASK 0xE000 // Refresh rate mask
+ #define VG_FRSH_REF_GO 0x1000 // Refresh rate GO bit
+ // Uses CFP_REF_xxx values from below
+ #define VG_FRSH_BPP_MASK 0x0E00 // Color depth mask
+ #define VG_FRSH_BPP_GO 0x0100 // Color depth GO bit
+ #define FRSH_BPP_8RGB 0x0200 // 8 bits per pixel, RGB
+ #define FRSH_BPP_16ARGB 0x0400 // 16BPP, ARGB (4:4:4:4)
+ #define FRSH_BPP_15RGB 0x0600 // 15BPP, RGB (1:5:5:5)
+ #define FRSH_BPP_16RGB 0x0800 // 16BPP, RGB (5:6:5)
+ #define FRSH_BPP_24RGB 0x0A00 // 24BPP, RGB (0:8:8:8)
+ #define FRSH_BPP_32ARGB 0x0C00 // 32BPP, ARGB (8:8:8:8)
+ #define VG_CFG_DPMS 0x00C0 // DPMS mask bits
+ #define VG_CFG_DPMS_H 0x0040 // HSYNC mask bit
+ #define VG_CFG_DPMS_V 0x0080 // VSYNC mask bit
+ #define VG_VESA_SV_RST 0x0020 // VESA Save/Restore state flag
+ #define VG_VESA_RST 0x0000 // VESA Restore state
+ #define VG_VESA_SV 0x0020 // VESA Save state
+ #define VG_FRSH_MODE 0x0002 // Mode refresh flag
+ #define VG_FRSH_TIMINGS 0x0001 // Timings only refresh flag
+
+ // Defined for GX2/SoftVG
+ #define VG_PLL_REF 0x01 // PLL reference frequency selection register
+ #define PLL_14MHZ 0x0000 // 14.31818MHz PLL reference frequency (Default)
+ #define PLL_48MHZ 0x0100 // 48MHz PLL reference frequency
+
+ // Defined for GX1/SoftVGA
+ #define VGA_MEM_SIZE 0x01 // bits 7:1 - 128K unit size, bit 0 controller enable
+
+ #define VG_FP_TYPE 0x02 // Flat panel type data
+ // VG_FP_TYPE definitions for GX2/SoftVG
+ #define FP_TYPE_SSTN 0x0000 // SSTN panel type value
+ #define FP_TYPE_DSTN 0x0001 // DSTN panel type value
+ #define FP_TYPE_TFT 0x0002 // TFT panel type value
+ #define FP_TYPE_LVDS 0x0003 // LVDS panel type value
+ #define FP_RES_6X4 0x0000 // 640x480 resolution value
+ #define FP_RES_8X6 0x0008 // 800x600 resolution value
+ #define FP_RES_10X7 0x0010 // 1024x768 resolution value
+ #define FP_RES_11X8 0x0018 // 1152x864 resolution value
+ #define FP_RES_12X10 0x0020 // 1280x1024 resolution value
+ #define FP_RES_16X12 0x0028 // 1600x1200 resolution value
+ #define FP_WIDTH_8 0x0000 // 8 bit data bus width
+ #define FP_WIDTH_9 0x0040 // 9 bit data bus width
+ #define FP_WIDTH_12 0x0080 // 12 bit data bus width
+ #define FP_WIDTH_18 0x00C0 // 18 bit data bus width
+ #define FP_WIDTH_24 0x0100 // 24 bit data bus width
+ #define FP_WIDTH_16 0x0140 // 16 bit data bus width - 16 bit Mono DSTN only
+ #define FP_COLOR_COLOR 0x0000 // Color panel
+ #define FP_COLOR_MONO 0x0200 // Mono Panel
+ #define FP_PPC_1PPC 0x0000 // One pixel per clock
+ #define FP_PPC_2PPC 0x0400 // Two pixels per clock
+ #define FP_H_POL_LGH 0x0000 // HSync at panel, normally low, active high
+ #define FP_H_POL_HGL 0x0800 // HSync at panel, normally high, active low
+ #define FP_V_POL_LGH 0x0000 // VSync at panel, normally low, active high
+ #define FP_V_POL_HGL 0x1000 // VSync at panel, normally high, active low
+ #define FP_REF_60 0x0000 // 60Hz refresh rate
+ #define FP_REF_65 0x2000 // 65Hz refresh rate
+ #define FP_REF_70 0x4000 // 70Hz refresh rate
+ #define FP_REF_72 0x6000 // 72Hz refresh rate
+ #define FP_REF_75 0x8000 // 75Hz refresh rate
+ #define FP_REF_85 0xA000 // 85Hz refresh rate
+
+ // VG_FP_TYPE definitions for GX3/GX3VG
+ #define FP_TYPE_TYPE 0x0003 // Flat panel type bits mask
+ #define CFP_TYPE_TFT 0x0000 // TFT panel type value
+ #define CFP_TYPE_LVDS 0x0001 // LVDS panel type value
+ #define FP_TYPE_RES 0x0038 // Panel resolution bits mask
+ #define CFP_RES_3X2 0x0000 // 320x240 resolution value
+ #define CFP_RES_6X4 0x0008 // 640x480 resolution value
+ #define CFP_RES_8X6 0x0010 // 800x600 resolution value
+ #define CFP_RES_10X7 0x0018 // 1024x768 resolution value
+ #define CFP_RES_11X8 0x0020 // 1152x864 resolution value
+ #define CFP_RES_12X10 0x0028 // 1280x1024 resolution value
+ #define CFP_RES_16X12 0x0030 // 1600x1200 resolution value
+ #define FP_TYPE_BUS 0x00C0 // Data bus width and pixels/clock mask
+ #define CFP_BUS_1PPC 0x0040 // 9, 12, 18 or 24 bit data bus, 1 pixel per clock
+ #define CFP_BUS_2PPC 0x0080 // 18 or 24 bit data bus, 2 pixels per clock
+ #define FP_TYPE_HPOL 0x0800 // HSYNC polarity into the panel
+ #define CFP_HPOL_HGL 0x0000 // HSync at panel, normally high, active low
+ #define CFP_HPOL_LGH 0x0800 // HSync at panel, normally low, active high
+ #define FP_TYPE_VPOL 0x1000 // VSYNC polarity into the panel
+ #define CFP_VPOL_HGL 0x0000 // VSync at panel, normally high, active low
+ #define CFP_VPOL_LGH 0x1000 // VSync at panel, normally low, active high
+ #define FP_TYPE_REF 0xE000 // Panel refresh rate
+ #define CFP_REF_60 0x0000 // 60Hz refresh rate
+ #define CFP_REF_70 0x2000 // 70Hz refresh rate
+ #define CFP_REF_75 0x4000 // 75Hz refresh rate
+ #define CFP_REF_85 0x6000 // 85Hz refresh rate
+ #define CFP_REF_100 0x8000 // 100Hz refresh rate
+
+ #define VG_FP_OPTION 0x03 // Flat panel option data
+ #define FP_OPT_SCLK_NORMAL 0x0000 // SHFTClk not inverted to panel
+ #define FP_OPT_SCLK_INVERTED 0x0010 // SHFTClk inverted to panel
+ #define FP_OPT_SCLK_ACT_ACTIVE 0x0000 // SHFTClk active during "active" only
+ #define FP_OPT_SCLK_ACT_FREE 0x0020 // SHFTClk free-running
+ #define FP_OPT_LP_ACT_FREE 0x0000 // LP free-running
+ #define FP_OPT_LP_ACT_ACTIVE 0x0040 // LP active during "active" only
+ #define FP_OPT_LDE_POL_LGH 0x0000 // LDE/MOD, normally low, active high
+ #define FP_OPT_LDE_POL_HGL 0x0080 // LDE/MOD, normally high, active low
+ #define FP_OPT_PWR_DLY_32MS 0x0000 // 32MS delay for each step of pwr seq.
+ #define FP_OPT_PWR_DLY_128MS 0x0100 // 128MS delay for each step of pwr seq.
+
+ #define VG_TV_CONFIG 0x04 // TV configuration register
+ #define VG_TV_ENC 0x000F // TV encoder select mask
+ #define VG_TV_ADV7171 0x0000 // ADV7171 Encoder
+ #define VG_TV_SAA7127 0x0001 // ADV7171 Encoder
+ #define VG_TV_ADV7300 0x0002 // ADV7300 Encoder
+ #define VG_TV_FS454 0x0003 // FS454 Encoder
+ #define VG_TV_FMT 0x0070 // TV encoder output format mask
+ #define VG_TV_FMT_SHIFT 0x0004 // Right shift value
+ #define VG_TV_NTSC 0x0000 // NTSC output format
+ #define VG_TV_PAL 0x0010 // PAL output format
+ #define VG_TV_HDTV 0x0020 // HDTV output format
+
+ // The meaning of the VG_TV_RES field is dependent on the selected
+ // encoder and output format. The translations are:
+ // ADV7171 - Not Used
+ // SAA7127 - Not Used
+ // ADV7300 - HDTV resolutions only
+ // LO -> 720x480p
+ // MED -> 1280x720p
+ // HI -> 1920x1080i
+ // FS454 - Both SD and HD resolutions
+ // SD Resolutions - NTSC and PAL
+ // LO -> 640x480
+ // MED -> 800x600
+ // HI -> 1024x768
+ // HD Resolutions
+ // LO -> 720x480p
+ // MED -> 1280x720p
+ // HI -> 1920x1080i
+ #define VG_TV_RES 0x0780 // TV resolution select mask
+ #define VG_TV_RES_SHIFT 0x0007 // Right shift value
+ #define VG_TV_RES_LO 0x0000 // Low resolution
+ #define VG_TV_RES_MED 0x0080 // Medium resolution
+ #define VG_TV_RES_HI 0x0100 // High resolution
+ #define VG_TV_PASSTHRU 0x0800 // TV passthru mode
+
+ #define VG_TV_SCALE_ADJ 0x05 // Modifies scaling factors for TV resolutions
+ #define VG_TV_HACT_ADJ 0x00FF // Horizontal active scale adjust value mask
+ #define VG_TV_VACT_ADJ 0xFF00 // Vertical active scale adjust value mask
+
+ #define VG_DEBUG 0x0F // A debug register
+
+ #define VG_FT_HTOT 0x10 // Fixed timings, horizontal total
+ #define VG_FT_HACT 0x11 // Fixed timings, horizontal active
+ #define VG_FT_HBST 0x12 // Fixed timings, horizontal blank start
+ #define VG_FT_HBND 0x13 // Fixed timings, horizontal blank end
+ #define VG_FT_HSST 0x14 // Fixed timings, horizontal sync start
+ #define VG_FT_HSND 0x15 // Fixed timings, horizontal sync end
+
+ #define VG_FT_VTOT 0x16 // Fixed timings, vertical total
+ #define VG_FT_VACT 0x17 // Fixed timings, vertical active
+ #define VG_FT_VBST 0x18 // Fixed timings, vertical blank start
+ #define VG_FT_VBND 0x19 // Fixed timings, vertical blank end
+ #define VG_FT_VSST 0x1A // Fixed timings, vertical sync start
+ #define VG_FT_VSND 0x1B // Fixed timings, vertical sync end
+
+ #define VG_START_OFFS_LO 0x20 // Framebuffer start offset bits 15:0
+ #define VG_START_OFFS_HI 0x21 // Framebuffer start offset bits 27:16
+
+ #define VG_FT_VEACT 0x28 // Fixed timings, vertical active
+ #define VG_FT_VETOT 0x29 // Fixed timings, vertical total
+ #define VG_FT_VEBST 0x2A // Fixed timings, vertical blank start
+ #define VG_FT_VEBND 0x2B // Fixed timings, vertical blank end
+ #define VG_FT_VESST 0x2C // Fixed timings, vertical sync start
+ #define VG_FT_VESND 0x2D // Fixed timings, vertical sync end
+
+ #define MAX_VGA VGA_MEM_SIZE
+// #define MAX_VG VG_FP_OPTION
+// #define MAX_VG VG_START_OFFS_HI
+ #define MAX_VG VG_FT_VESND
+
+#define VRC_APM 0x03
+ #define REPORT_EVENT 0x00
+ #define CAPABILITIES 0x01
+ #define APM_PRESENT 0x02
+ #define MAX_APM APM_PRESENT
+
+
+#define VRC_PM 0x04 // Legacy PM Class
+ #define POWER_MODE 0x00
+ #define POWER_STATE 0x01
+ #define DOZE_TIMEOUT 0x02
+ #define STANDBY_TIMEOUT 0x03
+ #define SUSPEND_TIMEOUT 0x04
+ #define PS2_TIMEOUT 0x05
+ #define RESUME_ON_RING 0x06
+ #define VIDEO_TIMEOUT 0x07
+ #define DISK_TIMEOUT 0x08
+ #define FLOPPY_TIMEOUT 0x09
+ #define SERIAL_TIMEOUT 0x0A
+ #define PARALLEL_TIMEOUT 0x0B
+ #define IRQ_WAKEUP_MASK 0x0C
+// #define SUSPEND_MODULATION 0x0D
+ #define SLEEP_PIN 0x0E
+ #define SLEEP_PIN_ATTR 0x0F
+// #define SMI_WAKEUP_MASK 0x10
+ #define INACTIVITY_CONTROL 0x11
+ #define PM_S1_CLOCKS 0x12
+ #define S1_CLOCKS_ON 0x00
+ #define S1_CLOCKS_OFF 0x01
+// #define PM_S2_CLOCKS 0x13
+// #define PM_S3_CLOCKS 0x14
+// #define PM_S4_CLOCKS 0x15
+// #define PM_S5_CLOCKS 0x16
+ #define PM_S0_LED 0x17
+ #define PM_S1_LED 0x18
+ #define PM_S2_LED 0x19
+ #define PM_S3_LED 0x1A
+ #define PM_S4_LED 0x1B
+ #define PM_S5_LED 0x1C
+ #define PM_LED_GPIO 0x1D
+ #define PM_IMM_LED 0x1E
+ #define PM_PWR_LEDS 0x1F
+ #define MB_LED0 0x01
+ #define MB_LED1 0x02
+ #define MB_LED2 0x04
+ #define MB_LED3 0x08
+ #define SIO_LED0 0x10
+ #define SIO_LED1 0x20
+ #define SIO_LED2 0x40
+ #define SIO_LED3 0x80
+ #define PM_PME_MASK 0x20
+ #define MAX_PM PM_PME_MASK
+
+
+#define VRC_INFRARED 0x05
+ #define MAX_INFRARED NO_VR
+
+#define VRC_TV 0x06 // TV Encoder Class
+ #define TV_ENCODER_TYPE 0x00
+ #define TV_CALLBACK_MASK 0x01
+ #define TV_MODE 0x02
+ #define TV_POSITION 0x03
+ #define TV_BRIGHTNESS 0x04
+ #define TV_CONTRAST 0x05
+ #define TV_OUTPUT 0x06
+ #define TV_TIMING 0x10 // 0x10...0x1D are all timings
+ #define MAX_TV TV_TIMING
+
+
+
+#define VRC_EXTERNAL_AMP 0x07
+ #define EAPD_VERSION 0x00
+ #define AMP_POWER 0x01
+ #define AMP_OFF 0x00
+ #define AMP_ON 0x01
+ #define AMP_TYPE 0x02
+ #define MAX_EXTERNAL_AMP AMP_TYPE
+
+
+#define VRC_ACPI 0x08
+ #define ENABLE_ACPI 0x00 // Enable ACPI Mode
+ #define SCI_IRQ 0x01 // Set the IRQ the SCI is mapped to, sysbios use.
+ #define ACPINVS_LO 0x02 // new calls to send 32bit physAddress of
+ #define ACPINVS_HI 0x03 // ACPI NVS region to VSA
+ #define GLOBAL_LOCK 0x04 // read requests semaphore, write clears
+ #define ACPI_UNUSED1 0x05
+ #define RW_PIRQ 0x06 // read/write PCI IRQ router regs in SB Func0 cfg space
+ #define SLPB_CLEAR 0x07 // clear sleep button GPIO status's
+ #define PIRQ_ROUTING 0x08 // read the PCI IRQ routing based on BIOS setup
+ #define ACPI_UNUSED2 0x09
+ #define ACPI_UNUSED3 0x0A
+ #define PIC_INTERRUPT 0x0B
+ #define ACPI_PRESENT 0x0C
+ #define ACPI_GEN_COMMAND 0x0D
+ #define ACPI_GEN_PARAM1 0x0E
+ #define ACPI_GEN_PARAM2 0x0F
+ #define ACPI_GEN_PARAM3 0x10
+ #define ACPI_GEN_RETVAL 0x11
+ #define MAX_ACPI ACPI_GEN_RETVAL
+
+#define VRC_ACPI_OEM 0x09
+ #define MAX_ACPI_OEM NO_VR
+
+#define VRC_POWER 0x0A
+ #define BATTERY_UNITS 0x00 // No. battery units
+ #define BATTERY_SELECT 0x01
+ #define AC_STATUS 0x02
+ #define BATTERY_STATUS 0x03
+ #define BATTERY_FLAG 0x04
+ #define BATTERY_PERCENTAGE 0x05
+ #define BATTERY_TIME 0x06
+ #define MAX_POWER BATTERY_TIME
+
+
+
+#define VRC_OHCI 0x0B // OHCI Class
+ #define SET_LED 0x00
+ #define INIT_OHCI 0x01
+ #define MAX_OHCI INIT_OHCI
+
+#define VRC_KEYBOARD 0x0C // Kbd Controller Class
+ #define KEYBOARD_PRESENT 0x00
+ #define SCANCODE 0x01
+ #define MOUSE_PRESENT 0x02
+ #define MOUSE_BUTTONS 0x03
+ #define MOUSE_XY 0x04
+ #define MAX_KEYBOARD MOUSE_XY
+
+
+#define VRC_DDC 0x0D // Video DDC Class
+ #define VRC_DDC_ENABLE 0x00 // Enable/disable register
+ #define DDC_DISABLE 0x00
+ #define DDC_ENABLE 0x01
+ #define VRC_DDC_IO 0x01 // A non-zero value for safety
+ #define MAX_DDC VRC_DDC_IO
+
+#define VRC_DEBUGGER 0x0E
+ #define MAX_DEBUGGER NO_VR
+
+
+#define VRC_STR 0x0F // Virtual Register class
+ #define RESTORE_ADDR 0x00 // Physical address of MSR restore table
+
+
+#define VRC_COP8 0x10 // Virtual Register class
+ #define VRC_HIB_ENABLE 0x00 // HIB enable/disable index
+ #define HIB_ENABLE 0x00 // HIB enable command
+ #define HIB_DISABLE 0x01 // HIB disable command
+ #define VRC_HIB_SEND 0x01 // Send packet to COP8
+ #define VRC_HIB_READUART 0x02 // Read byte from COP8 UART
+ #define VRC_HIB_VERSION 0x03 // Read COP8 version
+ #define VRC_HIB_SERIAL 0x04 // Read 8 byte serial number
+ #define VRC_HIB_USRBTN 0x05 // Read POST button pressed status
+ #define MAX_COP8 NO_VR
+
+#define VRC_OWL 0x11 // Virtual Register class
+ #define VRC_OWL_DAC 0x00 // DAC (Backlight) Control
+ #define VRC_OWL_GPIO 0x01 // GPIO Control
+ #define MAX_OWL VRC_OWL_GPIO
+
+#define VRC_SYSINFO 0x12 // Virtual Register class
+ #define VRC_SI_VERSION 0x00 // Sysinfo VSM version
+ #define VRC_SI_CPU_MHZ 0x01 // CPU speed in MHZ
+ #define VRC_SI_CHIPSET_BASE_LOW 0x02
+ #define VRC_SI_CHIPSET_BASE_HI 0x03
+ #define VRC_SI_CHIPSET_ID 0x04
+ #define VRC_SI_CHIPSET_REV 0x05
+ #define VRC_SI_CPU_ID 0x06
+ #define VRC_SI_CPU_REV 0x07
+ #define MAX_SYSINFO VRC_SI_CPU_REV
+
+#define VRC_SUPERIO 0x13
+ #define VRC_SIO_CHIPID 0x00
+ #define VRC_SIO_NUMLD 0x01
+ #define VRC_SIO_FDCEN 0x02
+ #define VRC_SIO_FDCIO 0x03
+ #define VRC_SIO_FDCIRQ 0x04
+ #define VRC_SIO_FDCDMA 0x05
+ #define VRC_SIO_FDCCFG1 0x06
+ #define VRC_SIO_FDCCFG2 0x07
+ #define VRC_SIO_PP1EN 0x08
+ #define VRC_SIO_PP1IO 0x09
+ #define VRC_SIO_PP1IRQ 0x0A
+ #define VRC_SIO_PP1DMA 0x0B
+ #define VRC_SIO_PP1CFG1 0x0C
+ #define VRC_SIO_SP1EN 0x0D
+ #define VRC_SIO_SP1IO 0x0E
+ #define VRC_SIO_SP1IRQ 0x0F
+ #define VRC_SIO_SP1CFG1 0x10
+ #define VRC_SIO_SP2EN 0x11
+ #define VRC_SIO_SP2IO 0x12
+ #define VRC_SIO_SP2IRQ 0x13
+ #define VRC_SIO_SP2CFG1 0x14
+ #define VRC_SIO_KBEN 0x15
+ #define VRC_SIO_KBIO1 0x16
+ #define VRC_SIO_KBIO2 0x17
+ #define VRC_SIO_KBIRQ 0x18
+ #define VRC_SIO_KBCFG1 0x19
+ #define VRC_SIO_MSEN 0x1A
+ #define VRC_SIO_MSIO 0x1B
+ #define VRC_SIO_MSIRQ 0x1C
+ #define VRC_SIO_RTCEN 0x1D
+ #define VRC_SIO_RTCIO1 0x1E
+ #define VRC_SIO_RTCIO2 0x1F
+ #define VRC_SIO_RTCIRQ 0x20
+ #define VRC_SIO_RTCCFG1 0x21
+ #define VRC_SIO_RTCCFG2 0x22
+ #define VRC_SIO_RTCCFG3 0x23
+ #define VRC_SIO_RTCCFG4 0x24
+ #define MAX_SUPERIO VRC_SIO_RTCCFG4
+
+#define VRC_CHIPSET 0x14
+ #define VRC_CS_PWRBTN 0x00
+ #define VRC_CS_UART1 0x01
+ #define VRC_CS_UART2 0x02
+ #define MAX_CHIPSET VRC_CS_UART2
+
+#define VRC_THERMAL 0x15
+ #define VRC_THERMAL_CURR_RTEMP 0x00 // read only
+ #define VRC_THERMAL_CURR_LTEMP 0x01 // read only
+ #define VRC_THERMAL_FAN 0x02
+ #define VRC_THERMAL_LOW_THRESHOLD 0x03
+ #define VRC_THERMAL_HIGH_THRESHOLD 0x04
+ #define VRC_THERMAL_INDEX 0x05
+ #define VRC_THERMAL_DATA 0x06
+ #define VRC_THERMAL_SMB_ADDRESS 0x07
+ #define VRC_THERMAL_SMB_INDEX 0x08
+ #define VRC_THERMAL_SMB_DATA 0x09
+ #define MAX_THERMAL VRC_THERMAL_SMB_DATA
+
+#define MAX_VR_CLASS VRC_THERMAL
diff --git a/src/mainboard/olpc/rev_a/Config.lb b/src/mainboard/olpc/rev_a/Config.lb
index db80ccd02a..0ab8e1e3ac 100644
--- a/src/mainboard/olpc/rev_a/Config.lb
+++ b/src/mainboard/olpc/rev_a/Config.lb
@@ -125,6 +125,7 @@ config chip.h
chip northbridge/amd/gx2
register "irqmap" = "0xaa5b"
+ register "setupflash" = "0"
device apic_cluster 0 on
chip cpu/amd/model_gx2
device apic 0 on end
@@ -147,7 +148,10 @@ chip northbridge/amd/gx2
device pci f.2 on end # IDE Controller
device pci f.3 on end # Audio
device pci f.4 on end # OHCI
- device pci f.5 on end # UHCI
+ device pci f.5 on end # EHCI
+ register "unwanted_vpci[0]" = "0x80007E00" # USB/UDC
+ register "unwanted_vpci[1]" = "0x80007F00" # USB/OTG
+ register "unwanted_vpci[2]" = "0" # End of list has a zero
end
end
end
diff --git a/src/northbridge/amd/gx2/chip.h b/src/northbridge/amd/gx2/chip.h
index 46e6ae87be..556c0e1de0 100644
--- a/src/northbridge/amd/gx2/chip.h
+++ b/src/northbridge/amd/gx2/chip.h
@@ -1,6 +1,7 @@
struct northbridge_amd_gx2_config
{
- uint16_t irqmap;
+ uint16_t irqmap;
+ int setupflash;
};
extern struct chip_operations northbridge_amd_gx2_ops;
diff --git a/src/northbridge/amd/gx2/chipsetinit.c b/src/northbridge/amd/gx2/chipsetinit.c
index a149d626ef..3bd73f7c9c 100644
--- a/src/northbridge/amd/gx2/chipsetinit.c
+++ b/src/northbridge/amd/gx2/chipsetinit.c
@@ -163,7 +163,90 @@ pmChipsetInit(void) {
}
+struct FLASH_DEVICE {
+ unsigned char fType; /* Flash type: NOR or NAND */
+ unsigned char fInterface; /* Flash interface: I/O or Memory */
+ unsigned long fMask; /* Flash size/mask */
+};
+
+struct FLASH_DEVICE FlashInitTable[] = {
+ { FLASH_TYPE_NAND, FLASH_IF_MEM, FLASH_MEM_4K }, /* CS0, or Flash Device 0 */
+ { FLASH_TYPE_NONE, 0, 0 }, /* CS1, or Flash Device 1 */
+ { FLASH_TYPE_NONE, 0, 0 }, /* CS2, or Flash Device 2 */
+ { FLASH_TYPE_NONE, 0, 0 }, /* CS3, or Flash Device 3 */
+};
+
+#define FlashInitTableLen (sizeof(FlashInitTable)/sizeof(FlashInitTable[0]))
+
+uint32_t FlashPort[] = {
+ MDD_LBAR_FLSH0,
+ MDD_LBAR_FLSH1,
+ MDD_LBAR_FLSH2,
+ MDD_LBAR_FLSH3
+ };
+
+/***************************************************************************
+ *
+ * ChipsetFlashSetup
+ *
+ * Flash LBARs need to be setup before VSA init so the PCI BARs have
+ * correct size info. Call this routine only if flash needs to be
+ * configured (don't call it if you want IDE).
+ *
+ * Entry:
+ * Exit:
+ * Destroys:
+ *
+ **************************************************************************/
+static void ChipsetFlashSetup(void)
+{
+ msr_t msr;
+ int i;
+ int numEnabled = 0;
+
+ printk_debug("ChipsetFlashSetup++\n");
+ for (i = 0; i < FlashInitTableLen; i++) {
+ if (FlashInitTable[i].fType != FLASH_TYPE_NONE) {
+ printk_debug("Enable CS%d\n", i);
+ /* we need to configure the memory/IO mask */
+ msr = rdmsr(FlashPort[i]);
+ msr.hi = 0; /* start with the "enabled" bit clear */
+ if (FlashInitTable[i].fType == FLASH_TYPE_NAND)
+ msr.hi |= 0x00000002;
+ else
+ msr.hi &= ~0x00000002;
+ if (FlashInitTable[i].fInterface == FLASH_IF_MEM)
+ msr.hi |= 0x00000004;
+ else
+ msr.hi &= ~0x00000004;
+ msr.hi |= FlashInitTable[i].fMask;
+ printk_debug("WRMSR(0x%08X, %08X_%08X)\n", FlashPort[i], msr.hi, msr.lo);
+ wrmsr(FlashPort[i], msr);
+
+ /* now write-enable the device */
+ msr = rdmsr(MDD_NORF_CNTRL);
+ msr.lo |= (1 << i);
+ printk_debug("WRMSR(0x%08X, %08X_%08X)\n", MDD_NORF_CNTRL, msr.hi, msr.lo);
+ wrmsr(MDD_NORF_CNTRL, msr);
+
+ /* update the number enabled */
+ numEnabled++;
+ }
+ }
+
+ /* enable the flash */
+ if (0 != numEnabled) {
+ msr = rdmsr(MDD_PIN_OPT);
+ msr.lo &= ~1; /* PIN_OPT_IDE */
+ printk_debug("WRMSR(0x%08X, %08X_%08X)\n", MDD_PIN_OPT, msr.hi, msr.lo);
+ wrmsr(MDD_PIN_OPT, msr);
+ }
+ printk_debug("ChipsetFlashSetup--\n");
+
+}
+
+
/* ***************************************************************************/
/* **/
/* * ChipsetGeodeLinkInit*/
@@ -202,7 +285,7 @@ ChipsetGeodeLinkInit(void){
}
void
-chipsetinit (void){
+chipsetinit (struct northbridge_amd_gx2_config *nb){
msr_t msr;
struct msrinit *csi;
int i;
@@ -275,8 +358,9 @@ chipsetinit (void){
/* Flash Setup*/
- printk_err("NOT DOING ChipsetFlashSetup()!!!!!!!!!!!!!!!!!!\n");
-// ChipsetFlashSetup();
+ printk_err("%sDOING ChipsetFlashSetup()!!!!!!!!!!!!!!!!!!\n", nb->setupflash? "NOT " : "");
+ if (nb->setupflash)
+ ChipsetFlashSetup();
diff --git a/src/northbridge/amd/gx2/grphinit.c b/src/northbridge/amd/gx2/grphinit.c
index 1d115c8c76..4e0da1789d 100644
--- a/src/northbridge/amd/gx2/grphinit.c
+++ b/src/northbridge/amd/gx2/grphinit.c
@@ -1,26 +1,32 @@
#include <arch/io.h>
#include <stdint.h>
-
+#include <cpu/amd/vr.h>
+
#define VIDEO_MB 8 // MB of video memory
-#define VRC_INDEX 0xAC1C // Index register
-#define VRC_DATA 0xAC1E // Data register
-#define VR_UNLOCK 0xFC53 // Virtual register unlock code
-#define VRC_VG 0x02 // SoftVG Class
-#define VG_MEM_SIZE 0x00 // bits 7:0 - 512K unit size, bit 8 controller priority
-
-
/*
* Write to a Virtual Register
* AX = Class/Index
* CX = data to write
*/
-static void vrWrite(uint16_t wClassIndex, uint16_t wData)
+void vrWrite(uint16_t wClassIndex, uint16_t wData)
{
outl(((uint32_t) VR_UNLOCK << 16) | wClassIndex, VRC_INDEX);
outw(wData, VRC_DATA);
}
+ /*
+ * Read from a Virtual Register
+ * AX = Class/Index
+ * Returns a 16-bit word of data
+ */
+uint16_t vrRead(uint16_t wClassIndex)
+{
+ uint16_t wData;
+ outl(((uint32_t) VR_UNLOCK << 16) | wClassIndex, VRC_INDEX);
+ wData = inw(VRC_DATA);
+ return wData;
+}
/*
* This function mirrors the Graphics_Init routine in GeodeROM.
diff --git a/src/northbridge/amd/gx2/northbridge.c b/src/northbridge/amd/gx2/northbridge.c
index 6ef9d55596..a0ad84669f 100644
--- a/src/northbridge/amd/gx2/northbridge.c
+++ b/src/northbridge/amd/gx2/northbridge.c
@@ -12,7 +12,7 @@
#include <cpu/amd/gx2def.h>
#include <cpu/x86/msr.h>
#include <cpu/x86/cache.h>
-
+#include <cpu/amd/vr.h>
#define VIDEO_MB 8
extern void graphics_init(void);
@@ -120,6 +120,28 @@ struct msr_defaults {
{0}
};
+/* note that dev is NOT used -- yet */
+static void irq_init_steering(struct device *dev, uint16_t irq_map) {
+ /* Set up IRQ steering */
+ uint32_t pciAddr = 0x80000000 | (CHIPSET_DEV_NUM << 11) | 0x5C;
+
+ printk_debug("%s(%08X [%08X], %04X)\n", __FUNCTION__, dev, pciAddr, irq_map);
+
+ /* The IRQ steering values (in hex) are effectively dcba, where:
+ * <a> represents the IRQ for INTA,
+ * <b> represents the IRQ for INTB,
+ * <c> represents the IRQ for INTC, and
+ * <d> represents the IRQ for INTD.
+ * Thus, a value of irq_map = 0xAA5B translates to:
+ * INTA = IRQB (IRQ 11)
+ * INTB = IRQ5 (IRQ 5)
+ * INTC = IRQA (IRQ 10)
+ * INTD = IRQA (IRQ 10)
+ */
+ outl(pciAddr & ~3, 0xCF8);
+ outl(irq_map, 0xCFC);
+}
+
/*
* setup_gx2_cache
@@ -198,11 +220,12 @@ setup_gx2(void)
msr.lo = 0x100 | ( ((membytes >>12) & 0xfff) << 20);
wrmsr(0x40000029, msr);
#endif
+#if 0
msr = rdmsr(0x10000028);
printk_debug("MSR 0x%x is now 0x%x:0x%x\n", 0x10000028, msr.hi,msr.lo);
msr = rdmsr(0x40000029);
printk_debug("MSR 0x%x is now 0x%x:0x%x\n", 0x40000029, msr.hi,msr.lo);
-
+#endif
#if 1
/* fixme: SMM MSR 0x10000026 and 0x400000023 */
/* calculate the OFFSET field */
@@ -253,9 +276,11 @@ static void enable_shadow(device_t dev)
static void northbridge_init(device_t dev)
{
+ struct northbridge_amd_gx2_config *nb = (struct northbridge_amd_gx2_config *)dev->chip_info;
printk_debug("northbridge: %s()\n", __FUNCTION__);
enable_shadow(dev);
+ irq_init_steering(dev, nb->irqmap);
}
static struct device_operations northbridge_operations = {
@@ -318,6 +343,7 @@ static void tolm_test(void *gp, struct device *dev, struct resource *new)
*best_p = best;
}
+#if 0
static uint32_t find_pci_tolm(struct bus *bus)
{
struct resource *min;
@@ -330,7 +356,7 @@ static uint32_t find_pci_tolm(struct bus *bus)
}
return tolm;
}
-
+#endif
#define FRAMEBUFFERK 4096
static void pci_domain_set_resources(device_t dev)
@@ -380,8 +406,8 @@ static void pci_domain_set_resources(device_t dev)
idx = 10;
ram_resource(dev, idx++, 0, tolmk);
}
- assign_resources(&dev->link[0]);
#endif
+ assign_resources(&dev->link[0]);
}
static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)
@@ -417,33 +443,13 @@ static struct device_operations cpu_bus_ops = {
void chipsetInit (void);
-/* note that dev is NOT used -- yet */
-static void irq_init(struct device *dev, uint16_t irq_map) {
-
- /* Set up IRQ steering */
- uint32_t pciAddr = 0x80000000 | (CHIPSET_DEV_NUM << 11) | 0x5C;
-
- printk_debug("OLPC REVA ENTER %s\n", __FUNCTION__);
-
- /* The IRQ steering values (in hex) are effectively dcba, where:
- * <a> represents the IRQ for INTA,
- * <b> represents the IRQ for INTB,
- * <c> represents the IRQ for INTC, and
- * <d> represents the IRQ for INTD.
- * Thus, a value of irq_map = 0xAA5B translates to:
- * INTA = IRQB (IRQ 11)
- * INTB = IRQ5 (IRQ 5)
- * INTC = IRQA (IRQ 10)
- * INTD = IRQA (IRQ 10)
- */
- outl(pciAddr & ~3, 0xCF8);
- outl(irq_map, 0xCFC);
-}
-
-
static void enable_dev(struct device *dev)
{
printk_debug("gx2 north: enable_dev\n");
+ void northbridgeinit(void);
+ void chipsetinit(struct northbridge_amd_gx2_config *nb);
+ void setup_realmode_idt(void);
+ void do_vsmbios(void);
/* Set the operations if it is a special bus type */
if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
struct northbridge_amd_gx2_config *nb = (struct northbridge_amd_gx2_config *)dev->chip_info;
@@ -452,12 +458,11 @@ static void enable_dev(struct device *dev)
/* cpubug MUST be called before setup_gx2(), so we force the issue here */
northbridgeinit();
cpubug();
- chipsetinit();
+ chipsetinit(nb);
setup_gx2();
/* do this here for now -- this chip really breaks our device model */
setup_realmode_idt();
do_vsmbios();
- irq_init(dev, nb->irqmap);
graphics_init();
dev->ops = &pci_domain_ops;
pci_set_method(dev);
diff --git a/src/southbridge/amd/cs5536/chip.h b/src/southbridge/amd/cs5536/chip.h
index c186ff31d7..1edb349ac7 100644
--- a/src/southbridge/amd/cs5536/chip.h
+++ b/src/southbridge/amd/cs5536/chip.h
@@ -1,6 +1,8 @@
#ifndef _SOUTHBRIDGE_AMD_CS5536
#define _SOUTHBRIDGE_AMD_CS5536
+#define MAX_UNWANTED_VPCI 10 /* increase if needed */
+
extern struct chip_operations southbridge_amd_cs5536_ops;
struct southbridge_amd_cs5536_config {
@@ -18,6 +20,8 @@ struct southbridge_amd_cs5536_config {
int usbf5_irq; /* f.5 */
int usbf6_irq; /* f.6 */
int usbf7_irq; /* f.7 */
+ /* the following allow you to disable unwanted virtualized PCI devices */
+ unsigned long unwanted_vpci[MAX_UNWANTED_VPCI];
};
#endif /* _SOUTHBRIDGE_AMD_CS5536 */
diff --git a/src/southbridge/amd/cs5536/cs5536.c b/src/southbridge/amd/cs5536/cs5536.c
index d5d0ae8255..9dcffd6fbc 100644
--- a/src/southbridge/amd/cs5536/cs5536.c
+++ b/src/southbridge/amd/cs5536/cs5536.c
@@ -9,22 +9,19 @@
#include <cpu/x86/msr.h>
#include "chip.h"
-static void southbridge_init(struct device *dev)
-{
- printk_err("cs5536: %s\n", __FUNCTION__);
- setup_i8259();
-}
-
#define PIN_OPT_IDE (1ULL<<0) /* 0 for flash, 1 for IDE */
/* Intended value for LBAR_FLSH0: 4KiB, enabled, MMIO, NAND, @0x20000000 */
+/* NOTE: no longer used, prune at some point */
msr_t flsh0 = { .hi=0xFFFFF007, .lo=0x20000000};
static void
enable_ide_nand_flash(){
msr_t msr;
printk_err("cs5536: %s\n", __FUNCTION__);
+#if 0
+ /* steve took this one out ... not sure if needed or not */
msr = rdmsr(MDD_LBAR_FLSH0);
if ( ((msr.hi) & 7) != 7) {
@@ -33,7 +30,7 @@ enable_ide_nand_flash(){
}
msr = rdmsr(MDD_LBAR_FLSH0);
printk_err("MDD_LBAR_FLSH0 is 0x%08x%08x\n", msr.hi,msr.lo);
-
+#endif
msr = rdmsr(MDD_PIN_OPT);
if (msr.lo & PIN_OPT_IDE) {
printk_err("MDD_PIN_OPT was 0x%08x%08x\n", msr.hi,msr.lo);
@@ -41,7 +38,7 @@ enable_ide_nand_flash(){
wrmsr(MDD_PIN_OPT, msr);
}
msr = rdmsr(MDD_PIN_OPT);
- printk_err("MDD_LBAR_FLSH0 is 0x%08x%08x\n", msr.hi,msr.lo);
+ printk_err("MDD_PIN_OPT is 0x%08x%08x\n", msr.hi,msr.lo);
msr = rdmsr(MDD_NANDF_DATA);
if (msr.lo != 0x00100010) {
@@ -63,6 +60,7 @@ enable_ide_nand_flash(){
printk_err("cs5536: EXIT %s\n", __FUNCTION__);
}
+#if 0
/* note: this is a candidate for inclusion in src/devices/pci_device.c */
void
setup_irq(unsigned irq, char *name, unsigned level, unsigned bus, unsigned device, unsigned fn){
@@ -78,17 +76,23 @@ setup_irq(unsigned irq, char *name, unsigned level, unsigned bus, unsigned devic
printk_err("%s: Can't find %s at 0x%x\n", __FUNCTION__, name, devfn);
}
}
+#endif
-static void southbridge_enable(struct device *dev)
+static void southbridge_init(struct device *dev)
{
struct southbridge_amd_cs5536_config *sb = (struct southbridge_amd_cs5536_config *)dev->chip_info;
- msr_t msr;
+ const unsigned char slots_cpu[4] = {11, 0, 0, 0};
+ const unsigned char slots_sb[4] = {11, 5, 10, 10};
+ msr_t msr;
+ int i;
/*
* struct device *gpiodev;
* unsigned short gpiobase = MDD_GPIO;
*/
- printk_err("%s: dev is %p\n", __FUNCTION__, dev);
+ printk_err("cs5536: %s\n", __FUNCTION__);
+ setup_i8259();
+
if (sb->lpc_serirq_enable) {
msr.lo = sb->lpc_serirq_enable;
msr.hi = 0;
@@ -114,30 +118,49 @@ static void southbridge_enable(struct device *dev)
}
if (sb->enable_uarta){
- printk_err("%s: enable uarta, msr MDD_IRQM_YHIGH(%x) \n",
+ printk_err("cs5536: %s: enable uarta, msr MDD_IRQM_YHIGH(%x) \n",
__FUNCTION__, MDD_IRQM_YHIGH);
msr = rdmsr(MDD_IRQM_YHIGH);
msr.lo |= 0x04000000;
wrmsr(MDD_IRQM_YHIGH, msr);
}
- printk_err("%s: enable_ide_nand_flash is %d\n", __FUNCTION__, sb->enable_ide_nand_flash);
+ printk_err("cs5536: %s: enable_ide_nand_flash is %d\n", __FUNCTION__, sb->enable_ide_nand_flash);
if (sb->enable_ide_nand_flash) {
enable_ide_nand_flash();
}
- /* irq handling */
- setup_irq(sb->audio_irq, "audio", 1, 0, 0xf, 2);
- setup_irq(sb->usbf4_irq, "usb f4", 1, 0, 0xf, 4);
- setup_irq(sb->usbf5_irq, "usb f5", 1, 0, 0xf, 5);
- setup_irq(sb->usbf6_irq, "usb f6", 1, 0, 0xf, 6);
- setup_irq(sb->usbf7_irq, "usb f7", 1, 0, 0xf, 7);
-
+#if 0
+ /* irq handling */
+ setup_irq(sb->audio_irq, "audio", 1, 0, 0xf, 2);
+ setup_irq(sb->usbf4_irq, "usb f4", 1, 0, 0xf, 4);
+ setup_irq(sb->usbf5_irq, "usb f5", 1, 0, 0xf, 5);
+ setup_irq(sb->usbf6_irq, "usb f6", 1, 0, 0xf, 6);
+ setup_irq(sb->usbf7_irq, "usb f7", 1, 0, 0xf, 7);
+#else
+ /* CPU (80000800 = 00.01.00) */
+ pci_assign_irqs(0, 0x01, slots_cpu); /* bus=0, device=0x01, slots={11,0,0,0} */
+
+ /* Southbridge (80007800 = 00.0F.00) */
+ pci_assign_irqs(0, 0x0F, slots_sb); /* bus=0, device=0x0F, slots={11,5,10,10} */
+#endif
+ /* disable unwanted virtual PCI devices */
+ for (i = 0; (i < MAX_UNWANTED_VPCI) && (0 != sb->unwanted_vpci[i]); i++) {
+ printk_debug("Disabling VPCI device: 0x%08X\n", sb->unwanted_vpci[i]);
+ outl(sb->unwanted_vpci[i] + 0x7C, 0xCF8);
+ outl(0xDEADBEEF, 0xCFC);
+ }
}
+
+static void southbridge_enable(struct device *dev)
+{
+ printk_err("cs5536: %s: dev is %p\n", __FUNCTION__, dev);
+ }
+
static void cs5536_pci_dev_enable_resources(device_t dev)
{
- printk_err("cs5536.c: %s()\n", __FUNCTION__);
+ printk_err("cs5536: %s()\n", __FUNCTION__);
pci_dev_enable_resources(dev);
enable_childrens_resources(dev);
}
@@ -147,7 +170,7 @@ static struct device_operations southbridge_ops = {
.set_resources = pci_dev_set_resources,
.enable_resources = cs5536_pci_dev_enable_resources,
.init = southbridge_init,
- .enable = southbridge_enable,
+// .enable = southbridge_enable,
.scan_bus = scan_static_bus,
};