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authorScott Duplichan <scott@notabs.org>2011-05-15 21:26:04 +0000
committerMarc Jones <marc.jones@amd.com>2011-05-15 21:26:04 +0000
commitdc312cca530940e4019bb3b0d9bbb97f9c748575 (patch)
tree1aacdfed1321efb2e22e711ca0a51ba478423f6d /src
parent2b9143afccef8ec9454914ab6d084c1630edb849 (diff)
downloadcoreboot-dc312cca530940e4019bb3b0d9bbb97f9c748575.tar.xz
Move mmconf base from e0000000 to f8000000 to avoid conflict with UMA BAR.
Signed-off-by: Scott Duplichan <scott@notabs.org> Acked-by: Marc Jones <marcj303@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6578 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src')
-rw-r--r--src/mainboard/amd/persimmon/dsdt.asl2
-rw-r--r--src/northbridge/amd/agesa_wrapper/family14/Kconfig4
-rw-r--r--src/vendorcode/amd/cimx/sb800/OEM.h2
3 files changed, 4 insertions, 4 deletions
diff --git a/src/mainboard/amd/persimmon/dsdt.asl b/src/mainboard/amd/persimmon/dsdt.asl
index 71a6189964..88730a7872 100644
--- a/src/mainboard/amd/persimmon/dsdt.asl
+++ b/src/mainboard/amd/persimmon/dsdt.asl
@@ -36,7 +36,7 @@ DefinitionBlock (
Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */
Name(PBLN, 0x0) /* Length of BIOS area */
- Name(PCBA, 0xE0000000) /* Base address of PCIe config space */
+ Name(PCBA, 0xF8000000) /* Base address of PCIe config space */
Name(HPBA, 0xFED00000) /* Base address of HPET table */
Name(SSFG, 0x0D) /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */
diff --git a/src/northbridge/amd/agesa_wrapper/family14/Kconfig b/src/northbridge/amd/agesa_wrapper/family14/Kconfig
index 015f1d1e66..fe36b89edd 100644
--- a/src/northbridge/amd/agesa_wrapper/family14/Kconfig
+++ b/src/northbridge/amd/agesa_wrapper/family14/Kconfig
@@ -41,12 +41,12 @@ config HW_MEM_HOLE_SIZE_AUTO_INC
config MMCONF_BASE_ADDRESS
hex
- default 0xe0000000
+ default 0xf8000000
depends on NORTHBRIDGE_AMD_AGESA_WRAPPER_FAMILY14
config MMCONF_BUS_NUMBER
int
- default 256
+ default 16
depends on NORTHBRIDGE_AMD_AGESA_WRAPPER_FAMILY14
config DIMM_DDR3
diff --git a/src/vendorcode/amd/cimx/sb800/OEM.h b/src/vendorcode/amd/cimx/sb800/OEM.h
index c3651e403b..6a79f325a1 100644
--- a/src/vendorcode/amd/cimx/sb800/OEM.h
+++ b/src/vendorcode/amd/cimx/sb800/OEM.h
@@ -48,7 +48,7 @@
#ifdef MOVE_PCIEBAR_TO_F0000000
#define PCIEX_BASE_ADDRESS 0xF7000000
#else
- #define PCIEX_BASE_ADDRESS 0xE0000000
+ #define PCIEX_BASE_ADDRESS 0xF8000000
#endif
/**