diff options
| author | Aaron Durbin <adurbin@chromium.org> | 2017-05-25 09:36:06 -0500 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-05-27 16:57:18 +0200 |
| commit | dd82edc388fe070fe35f862cf6ceeb86a62e1259 (patch) | |
| tree | 601d7c27a8cd4c8b2101016fbb3dd7502c833153 /src | |
| parent | c96f757af1e7f2cbeec5f7b215b561e638ec74e3 (diff) | |
| download | coreboot-dd82edc388fe070fe35f862cf6ceeb86a62e1259.tar.xz | |
lib/spd_bin: make SMBus SPD addresses an input
Instead of assuming the mapping of dimm number to SPD SMBus address,
allow the mainboard to provide its own mapping. That way, global
resources of empty SPD contents aren't wasted in order to address
a dimm on a mainboard that doesn't meet the current assumption.
Change-Id: Id0e79231dc2303373badaae003038a1ac06a5635
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/19915
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Naresh Solanki <naresh.solanki@intel.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/include/spd_bin.h | 1 | ||||
| -rw-r--r-- | src/lib/spd_bin.c | 2 | ||||
| -rw-r--r-- | src/mainboard/google/fizz/romstage.c | 4 | ||||
| -rw-r--r-- | src/mainboard/intel/kblrvp/romstage.c | 4 |
4 files changed, 8 insertions, 3 deletions
diff --git a/src/include/spd_bin.h b/src/include/spd_bin.h index 4d5ce2fb93..3783fafb4c 100644 --- a/src/include/spd_bin.h +++ b/src/include/spd_bin.h @@ -43,6 +43,7 @@ #define LPDDR4_SPD_PART_LEN 20 struct spd_block { + u8 addr_map[CONFIG_DIMM_MAX]; u8 *spd_array[CONFIG_DIMM_MAX]; /* Length of each dimm */ u16 len; diff --git a/src/lib/spd_bin.c b/src/lib/spd_bin.c index 5c4f09f858..3e26004a63 100644 --- a/src/lib/spd_bin.c +++ b/src/lib/spd_bin.c @@ -159,7 +159,7 @@ void get_spd_smbus(struct spd_block *blk) for (i = 0 ; i < CONFIG_DIMM_MAX; i++) { get_spd(spd_data_ptr + i * CONFIG_DIMM_SPD_SIZE, - 0xA0 + (i << 1)); + blk->addr_map[i]); blk->spd_array[i] = spd_data_ptr + i * CONFIG_DIMM_SPD_SIZE; } diff --git a/src/mainboard/google/fizz/romstage.c b/src/mainboard/google/fizz/romstage.c index be1d552156..4c816df55f 100644 --- a/src/mainboard/google/fizz/romstage.c +++ b/src/mainboard/google/fizz/romstage.c @@ -31,7 +31,9 @@ void mainboard_memory_init_params(FSPM_UPD *mupd) memcpy(&mem_cfg->RcompTarget, rcomp_target, sizeof(rcomp_target)); /* Read spd block to get memory config */ - struct spd_block blk; + struct spd_block blk = { + .addr_map = { 0xa0, 0xa4, }, + }; mem_cfg->DqPinsInterleaved = 1; get_spd_smbus(&blk); mem_cfg->MemorySpdDataLen = blk.len; diff --git a/src/mainboard/intel/kblrvp/romstage.c b/src/mainboard/intel/kblrvp/romstage.c index a3b1ba1f91..9082254385 100644 --- a/src/mainboard/intel/kblrvp/romstage.c +++ b/src/mainboard/intel/kblrvp/romstage.c @@ -50,7 +50,9 @@ void mainboard_memory_init_params(FSPM_UPD *mupd) /* Memory leak is ok since we have memory mapped boot media */ mem_cfg->MemorySpdPtr00 = (uintptr_t)rdev_mmap_full(&spd_rdev); } else { /* for CONFIG_BOARD_INTEL_KBLRVP7 */ - struct spd_block blk; + struct spd_block blk = { + .addr_map = { 0xa0, 0xa2, 0xa4, 0xa6, }, + }; mem_cfg->DqPinsInterleaved = 1; get_spd_smbus(&blk); |