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authorUwe Hermann <uwe@hermann-uwe.de>2010-10-14 23:40:10 +0000
committerUwe Hermann <uwe@hermann-uwe.de>2010-10-14 23:40:10 +0000
commite49903650cbb8a924a18bcfa28b270f79ef398a1 (patch)
tree7de2ea1c0cc2e074c255ecbff884d3efb0e96e2b /src
parent212d0a2eaefac97c55ad932e775be68a975fe164 (diff)
downloadcoreboot-e49903650cbb8a924a18bcfa28b270f79ef398a1.tar.xz
Cosmetics in ioapic.c (trivial, no functional changes).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5952 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src')
-rw-r--r--src/arch/i386/lib/ioapic.c42
1 files changed, 23 insertions, 19 deletions
diff --git a/src/arch/i386/lib/ioapic.c b/src/arch/i386/lib/ioapic.c
index d6616f5529..e39fe8fd0a 100644
--- a/src/arch/i386/lib/ioapic.c
+++ b/src/arch/i386/lib/ioapic.c
@@ -34,7 +34,6 @@ static void io_apic_write(u32 ioapic_base, u32 reg, u32 value)
write32(ioapic_base + 0x10, value);
}
-
void clear_ioapic(u32 ioapic_base)
{
u32 low, high;
@@ -42,8 +41,8 @@ void clear_ioapic(u32 ioapic_base)
printk(BIOS_DEBUG, "IOAPIC: Clearing IOAPIC at 0x%08x\n", ioapic_base);
- /* Read the available number of interrupts */
- ioapic_interrupts = (io_apic_read(ioapic_base, 1) >> 16) & 0xff;
+ /* Read the available number of interrupts. */
+ ioapic_interrupts = (io_apic_read(ioapic_base, 0x01) >> 16) & 0xff;
if (!ioapic_interrupts || ioapic_interrupts == 0xff)
ioapic_interrupts = 24;
printk(BIOS_DEBUG, "IOAPIC: %d interrupts\n", ioapic_interrupts);
@@ -55,11 +54,12 @@ void clear_ioapic(u32 ioapic_base)
io_apic_write(ioapic_base, i * 2 + 0x10, low);
io_apic_write(ioapic_base, i * 2 + 0x11, high);
- printk(BIOS_SPEW, "IOAPIC: reg 0x%08x value 0x%08x 0x%08x\n", i, high, low);
+ printk(BIOS_SPEW, "IOAPIC: reg 0x%08x value 0x%08x 0x%08x\n",
+ i, high, low);
}
if (io_apic_read(ioapic_base, 0x10) == 0xffffffff) {
- printk(BIOS_WARNING, "IO APIC not responding.\n");
+ printk(BIOS_WARNING, "IOAPIC not responding.\n");
return;
}
}
@@ -70,25 +70,25 @@ void setup_ioapic(u32 ioapic_base, u8 ioapic_id)
u32 low, high;
u32 i, ioapic_interrupts;
- printk(BIOS_DEBUG, "IOAPIC: Initializing IOAPIC at 0x%08x\n", ioapic_base);
- printk(BIOS_DEBUG, "IOAPIC: Bootstrap Processor Local APIC = %02x\n",
- bsp_lapicid);
+ printk(BIOS_DEBUG, "IOAPIC: Initializing IOAPIC at 0x%08x\n",
+ ioapic_base);
+ printk(BIOS_DEBUG, "IOAPIC: Bootstrap Processor Local APIC = 0x%02x\n",
+ bsp_lapicid);
if (ioapic_id) {
printk(BIOS_DEBUG, "IOAPIC: ID = 0x%02x\n", ioapic_id);
- /* Set IOAPIC ID if it has been specified */
+ /* Set IOAPIC ID if it has been specified. */
io_apic_write(ioapic_base, 0x00,
(io_apic_read(ioapic_base, 0x00) & 0xfff0ffff) |
- (ioapic_id << 24));
+ (ioapic_id << 24));
}
- /* Read the available number of interrupts */
- ioapic_interrupts = (io_apic_read(ioapic_base, 1) >> 16) & 0xff;
+ /* Read the available number of interrupts. */
+ ioapic_interrupts = (io_apic_read(ioapic_base, 0x01) >> 16) & 0xff;
if (!ioapic_interrupts || ioapic_interrupts == 0xff)
ioapic_interrupts = 24;
printk(BIOS_DEBUG, "IOAPIC: %d interrupts\n", ioapic_interrupts);
-
// XXX this decision should probably be made elsewhere, and
// it's the C3, not the EPIA this depends on.
#if defined(CONFIG_EPIA_VT8237R_INIT) && CONFIG_EPIA_VT8237R_INIT
@@ -98,18 +98,20 @@ void setup_ioapic(u32 ioapic_base, u8 ioapic_id)
#endif
#ifdef IOAPIC_INTERRUPTS_ON_FSB
- /* For the Pentium 4 and above APICs deliver their interrupts
+ /*
+ * For the Pentium 4 and above APICs deliver their interrupts
* on the front side bus, enable that.
*/
printk(BIOS_DEBUG, "IOAPIC: Enabling interrupts on FSB\n");
- io_apic_write(ioapic_base, 0x03, io_apic_read(ioapic_base, 0x03) | (1 << 0));
+ io_apic_write(ioapic_base, 0x03,
+ io_apic_read(ioapic_base, 0x03) | (1 << 0));
#endif
#ifdef IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS
printk(BIOS_DEBUG, "IOAPIC: Enabling interrupts on APIC serial bus\n");
io_apic_write(ioapic_base, 0x03, 0);
#endif
- /* Enable Virtual Wire Mode */
+ /* Enable Virtual Wire Mode. */
low = ENABLED | TRIGGER_EDGE | POLARITY_HIGH | PHYSICAL_DEST | ExtINT;
high = bsp_lapicid << (56 - 32);
@@ -117,11 +119,12 @@ void setup_ioapic(u32 ioapic_base, u8 ioapic_id)
io_apic_write(ioapic_base, 0x11, high);
if (io_apic_read(ioapic_base, 0x10) == 0xffffffff) {
- printk(BIOS_WARNING, "IO APIC not responding.\n");
+ printk(BIOS_WARNING, "IOAPIC not responding.\n");
return;
}
- printk(BIOS_SPEW, "IOAPIC: reg 0x%08x value 0x%08x 0x%08x\n", 0, high, low);
+ printk(BIOS_SPEW, "IOAPIC: reg 0x%08x value 0x%08x 0x%08x\n",
+ 0, high, low);
low = DISABLED;
high = NONE;
@@ -130,6 +133,7 @@ void setup_ioapic(u32 ioapic_base, u8 ioapic_id)
io_apic_write(ioapic_base, i * 2 + 0x10, low);
io_apic_write(ioapic_base, i * 2 + 0x11, high);
- printk(BIOS_SPEW, "IOAPIC: reg 0x%08x value 0x%08x 0x%08x\n", i, high, low);
+ printk(BIOS_SPEW, "IOAPIC: reg 0x%08x value 0x%08x 0x%08x\n",
+ i, high, low);
}
}