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authorpchandri <preetham.chandrian@intel.com>2015-09-14 14:11:38 -0700
committerPatrick Georgi <pgeorgi@google.com>2015-10-27 15:15:30 +0100
commite57e72681fa218bb747f658576c64111c20363e3 (patch)
tree380bf4a6c7488c2c5f3b0818289d7e152c2a7e69 /src
parentb45dde0b78cbe646e12316408ac67cdc72ed9a9d (diff)
downloadcoreboot-e57e72681fa218bb747f658576c64111c20363e3.tar.xz
intel/kunimitsu Fab3: Strengthening Rcomp target CTRL value
This patch strengthens the Rcomp Target CTRL by 10% for 8GB memory part K4E6E304EE-EGCF as with the current values the MRC training is failing due to more load on CS# BRANCH=None BUG=chrome-os-partner:44647 TEST=BUilds and boots on Kunimitsu. Change-Id: I478002bbebabaac418356d4b5b4755bb56009268 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: b208659e690d8cb5b8dcaf30eed53c01b9f77f6d Original-Change-Id: Ia0a0c1358649af77a3a0d301cb791f26f1e039bf Original-Signed-off-by: pchandri <preetham.chandrian@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/304103 Original-Commit-Ready: Preetham Chandrian <preetham.chandrian@intel.com> Original-Tested-by: Preetham Chandrian <preetham.chandrian@intel.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Preetham Chandrian <preetham.chandrian@intel.com> Reviewed-on: http://review.coreboot.org/12143 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src')
-rw-r--r--src/mainboard/intel/kunimitsu/pei_data.c18
-rw-r--r--src/mainboard/intel/kunimitsu/romstage.c12
-rw-r--r--src/mainboard/intel/kunimitsu/spd/spd.c11
-rw-r--r--src/soc/intel/skylake/include/soc/pei_data.h1
4 files changed, 28 insertions, 14 deletions
diff --git a/src/mainboard/intel/kunimitsu/pei_data.c b/src/mainboard/intel/kunimitsu/pei_data.c
index f7525daf2e..4bfc2f3bea 100644
--- a/src/mainboard/intel/kunimitsu/pei_data.c
+++ b/src/mainboard/intel/kunimitsu/pei_data.c
@@ -22,6 +22,11 @@
#include <string.h>
#include <soc/pei_data.h>
#include <soc/pei_wrapper.h>
+#include "boardid.h"
+
+/* PCH_MEM_CFG[3:0] */
+#define MAX_MEMORY_CONFIG 0x10
+#define RCOMP_TARGET_PARAMS 0x5
void mainboard_fill_pei_data(struct pei_data *pei_data)
{
@@ -40,12 +45,19 @@ void mainboard_fill_pei_data(struct pei_data *pei_data)
const u16 RcompResistor[3] = { 200, 81, 162 };
/* Rcomp target */
- const u16 RcompTarget[5] = { 100, 40, 40, 23, 40 };
+ static const u16 RcompTarget[MAX_MEMORY_CONFIG][RCOMP_TARGET_PARAMS] = {
+ { 100, 40, 40, 23, 40 },
+ { 100, 40, 40, 23, 40 },
+ { 100, 40, 40, 23, 40 },
+ /*Strengthen the Rcomp Target Ctrl for 8GB K4E6E304EE -EGCF*/
+ { 100, 40, 40, 21, 40 }, };
+
memcpy(pei_data->dq_map, dq_map, sizeof(dq_map));
memcpy(pei_data->dqs_map, dqs_map, sizeof(dqs_map));
memcpy(pei_data->RcompResistor, RcompResistor,
sizeof(RcompResistor));
- memcpy(pei_data->RcompTarget, RcompTarget,
- sizeof(RcompTarget));
+ memcpy(pei_data->RcompTarget, &RcompTarget[pei_data->mem_cfg_id][0],
+ sizeof(RcompTarget[pei_data->mem_cfg_id]));
+
}
diff --git a/src/mainboard/intel/kunimitsu/romstage.c b/src/mainboard/intel/kunimitsu/romstage.c
index a0eeafc9a5..cd855d681d 100644
--- a/src/mainboard/intel/kunimitsu/romstage.c
+++ b/src/mainboard/intel/kunimitsu/romstage.c
@@ -23,7 +23,7 @@
#include <console/console.h>
#include <string.h>
#include <ec/google/chromeec/ec.h>
-#include <soc/gpio.h>
+#include <gpio.h>
#include <soc/pei_data.h>
#include <soc/pei_wrapper.h>
#include <soc/romstage.h>
@@ -40,11 +40,21 @@ static void early_config_gpio(void)
void mainboard_romstage_entry(struct romstage_params *params)
{
+ /* PCH_MEM_CFG[3:0] */
+ gpio_t spd_gpios[] = {
+ GPIO_MEM_CONFIG_0,
+ GPIO_MEM_CONFIG_1,
+ GPIO_MEM_CONFIG_2,
+ GPIO_MEM_CONFIG_3,
+ };
+
/* Ensure the EC and PD are in the right mode for recovery */
google_chromeec_early_init();
early_config_gpio();
+ params->pei_data->mem_cfg_id = gpio_base2_value(spd_gpios,
+ ARRAY_SIZE(spd_gpios));
/* Fill out PEI DATA */
mainboard_fill_pei_data(params->pei_data);
mainboard_fill_spd_data(params->pei_data);
diff --git a/src/mainboard/intel/kunimitsu/spd/spd.c b/src/mainboard/intel/kunimitsu/spd/spd.c
index b8e0be6545..0deac2fe8c 100644
--- a/src/mainboard/intel/kunimitsu/spd/spd.c
+++ b/src/mainboard/intel/kunimitsu/spd/spd.c
@@ -22,14 +22,11 @@
#include <boardid.h>
#include <cbfs.h>
#include <console/console.h>
-#include <gpio.h>
-#include <soc/gpio.h>
#include <soc/pei_data.h>
#include <soc/romstage.h>
#include <string.h>
#include "../boardid.h"
-#include "../gpio.h"
#include "spd.h"
static void mainboard_print_spd_info(uint8_t spd[])
@@ -90,14 +87,8 @@ void mainboard_fill_spd_data(struct pei_data *pei_data)
size_t spd_file_len;
int spd_index, sku_id;
- gpio_t spd_gpios[] = {
- GPIO_MEM_CONFIG_0,
- GPIO_MEM_CONFIG_1,
- GPIO_MEM_CONFIG_2,
- GPIO_MEM_CONFIG_3,
- };
- spd_index = gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios));
+ spd_index = pei_data->mem_cfg_id;
/*
* XXX: This is incorrect usage.The Board ID should be the revision ID
* and not SKU ID but on SCRD it indicates SKU.
diff --git a/src/soc/intel/skylake/include/soc/pei_data.h b/src/soc/intel/skylake/include/soc/pei_data.h
index 2773051c03..be8ba79b92 100644
--- a/src/soc/intel/skylake/include/soc/pei_data.h
+++ b/src/soc/intel/skylake/include/soc/pei_data.h
@@ -91,6 +91,7 @@ struct pei_data {
/* Data from MRC that should be saved to flash */
void *data_to_save;
int data_to_save_size;
+ int mem_cfg_id;
} __attribute__((packed));
typedef struct pei_data PEI_DATA;