diff options
| author | Rizwan Qureshi <rizwan.qureshi@intel.com> | 2019-02-26 18:12:05 +0530 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-02-27 11:04:40 +0000 |
| commit | e64c25ca1a550132e1ad35208d6a71d553d57879 (patch) | |
| tree | 9e906683553e3d6d3ce23e4e5d3405c1d1b7a706 /src | |
| parent | 51749b276644f6e74c0f9e90647a0f752ac627d3 (diff) | |
| download | coreboot-e64c25ca1a550132e1ad35208d6a71d553d57879.tar.xz | |
soc/intel/cannonlake: Add ASL functions to manipulate RX/TX buffers
Add a function in gpio ASL library to enable/disable pad Rx/Tx Buffers.
BUG=b:123350329
Change-Id: I6c40d79debb61b0c4e96e485b410d446b77d9cf6
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/c/31619
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/intel/cannonlake/acpi/gpio_op.asl | 44 | ||||
| -rw-r--r-- | src/soc/intel/cannonlake/include/soc/gpio_defs.h | 4 | ||||
| -rw-r--r-- | src/soc/intel/cannonlake/include/soc/gpio_defs_cnp_h.h | 4 |
3 files changed, 52 insertions, 0 deletions
diff --git a/src/soc/intel/cannonlake/acpi/gpio_op.asl b/src/soc/intel/cannonlake/acpi/gpio_op.asl index 0c89e998c1..b024367181 100644 --- a/src/soc/intel/cannonlake/acpi/gpio_op.asl +++ b/src/soc/intel/cannonlake/acpi/gpio_op.asl @@ -94,3 +94,47 @@ Method (GPMO, 2, Serialized) And (ShiftLeft (Arg1, GPIOPADMODE_SHIFT, Arg1), GPIOPADMODE_MASK, Arg1) Or (Local0, Arg1, VAL0) } + +/* + * Enable/Disable Tx buffer + * Arg0 - GPIO Number + * Arg1 - TxBuffer state + * 0 = Disable Tx Buffer + * 1 = Enable Tx Buffer + */ +Method (GTXE, 2, Serialized) +{ + OperationRegion (PREG, SystemMemory, GADD (Arg0), 4) + Field (PREG, AnyAcc, NoLock, Preserve) + { + VAL0, 32 + } + + If (LEqual (Arg1, 1)) { + And (Not (GPIOTXBUFDIS_MASK), VAL0, VAL0) + } ElseIf (LEqual (Arg1, 0)){ + Or (GPIOTXBUFDIS_MASK, VAL0, VAL0) + } +} + +/* + * Enable/Disable Rx buffer + * Arg0 - GPIO Number + * Arg1 - RxBuffer state + * 0 = Disable Rx Buffer + * 1 = Enable Rx Buffer + */ +Method (GRXE, 2, Serialized) +{ + OperationRegion (PREG, SystemMemory, GADD (Arg0), 4) + Field (PREG, AnyAcc, NoLock, Preserve) + { + VAL0, 32 + } + + If (LEqual (Arg1, 1)) { + And (Not (GPIORXBUFDIS_MASK), VAL0, VAL0) + } ElseIf (LEqual (Arg1, 0)){ + Or (GPIORXBUFDIS_MASK, VAL0, VAL0) + } +} diff --git a/src/soc/intel/cannonlake/include/soc/gpio_defs.h b/src/soc/intel/cannonlake/include/soc/gpio_defs.h index e8b4f614ea..3399526cff 100644 --- a/src/soc/intel/cannonlake/include/soc/gpio_defs.h +++ b/src/soc/intel/cannonlake/include/soc/gpio_defs.h @@ -255,4 +255,8 @@ #define GPIOTXSTATE_MASK 0x1 #define GPIOPADMODE_MASK 0xC00 #define GPIOPADMODE_SHIFT 10 +#define GPIOTXBUFDIS_MASK 0x100 +#define GPIOTXBUFDIS_SHIFT 8 +#define GPIORXBUFDIS_MASK 0x200 +#define GPIORXBUFDIS_SHIFT 9 #endif diff --git a/src/soc/intel/cannonlake/include/soc/gpio_defs_cnp_h.h b/src/soc/intel/cannonlake/include/soc/gpio_defs_cnp_h.h index c74c2d7c96..c7f3c816ba 100644 --- a/src/soc/intel/cannonlake/include/soc/gpio_defs_cnp_h.h +++ b/src/soc/intel/cannonlake/include/soc/gpio_defs_cnp_h.h @@ -329,4 +329,8 @@ #define GPIOTXSTATE_MASK 0x1 #define GPIOPADMODE_MASK 0xC00 #define GPIOPADMODE_SHIFT 10 +#define GPIOTXBUFDIS_MASK 0x100 +#define GPIOTXBUFDIS_SHIFT 8 +#define GPIORXBUFDIS_MASK 0x200 +#define GPIORXBUFDIS_SHIFT 9 #endif |