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| author | Rizwan Qureshi <rizwan.qureshi@intel.com> | 2017-09-06 19:08:23 +0530 |
|---|---|---|
| committer | Furquan Shaikh <furquan@google.com> | 2017-09-15 18:20:42 +0000 |
| commit | ea4649f65fece2e14a3f2b0d1b4f5835a76a1141 (patch) | |
| tree | 5dc385e517c6832be5b5986bde4434300ca4d44c /src | |
| parent | 6a051f2b49d5d4b9605f4a4a2dfe46cd770704b3 (diff) | |
| download | coreboot-ea4649f65fece2e14a3f2b0d1b4f5835a76a1141.tar.xz | |
mb/google/poppy: enable AER for PCIe root port 0
Enable PCIe Advanced Error Reporting for PCIe root port 0.
BUG=b:64798078
TEST="lspci" shows that AER is enabled in the capabilities list.
Change-Id: I8a818a9539b8d4f103d551ffd59713c9bbbc13ce
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/21425
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/mainboard/google/poppy/variants/baseboard/devicetree.cb | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb index 5b81fc0d49..0bd2efc92c 100644 --- a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb @@ -152,6 +152,8 @@ chip soc/intel/skylake register "PcieRpClkReqSupport[0]" = "1" # RP 1 uses SRCCLKREQ1# register "PcieRpClkReqNumber[0]" = "1" + # RP 1, Enable Advanced Error Reporting + register PcieRpAdvancedErrorReporting[0] = "1" register "usb2_ports[0]" = "USB2_PORT_LONG(OC0)" # Type-C Port 1 register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port |