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authorElyes HAOUAS <ehaouas@noos.fr>2021-02-05 20:12:27 +0100
committerPatrick Georgi <pgeorgi@google.com>2021-02-09 07:46:47 +0000
commiteb26530e2c514ba0b1302dbbabe0954605d90539 (patch)
tree5b27bd691741b1f052366e6d2b0b06b23fc05606 /src
parente20a2b442710e56bae43cefb87936af6ca7979be (diff)
downloadcoreboot-eb26530e2c514ba0b1302dbbabe0954605d90539.tar.xz
sb/amd/pi/hudson/acpi/lpc.asl: Convert to ASL 2.0
Change-Id: Id50b9a0f0e3f90f5288b420280d762b8a86a6527 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50326 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src')
-rw-r--r--src/southbridge/amd/pi/hudson/acpi/lpc.asl4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/southbridge/amd/pi/hudson/acpi/lpc.asl b/src/southbridge/amd/pi/hudson/acpi/lpc.asl
index c7c7cb0244..41c3a7abc6 100644
--- a/src/southbridge/amd/pi/hudson/acpi/lpc.asl
+++ b/src/southbridge/amd/pi/hudson/acpi/lpc.asl
@@ -28,8 +28,8 @@ Device(LIBR) {
{
CreateDwordField(^CRS,^BAR0._BAS,SPIB) // Field to hold SPI base address
CreateDwordField(^CRS,^BAR0._LEN,SPIL) // Field to hold SPI address length
- Store(BAR,SPIB) // SPI base address mapped
- Store(0x1000,SPIL) // 4k space mapped
+ SPIB = BAR // SPI base address mapped
+ SPIL = 0x1000 // 4k space mapped
Return(CRS)
}
}