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authorKyösti Mälkki <kyosti.malkki@gmail.com>2018-01-15 17:52:58 +0200
committerKyösti Mälkki <kyosti.malkki@gmail.com>2018-01-24 02:08:51 +0000
commiteb7e6b5c8160f5edfda1ac080ab77c1ba2c48306 (patch)
tree419a2c2aaa29d8680c57b1fff34a9a0f6f886111 /src
parent63278ab07d684f90804065a6351e0d138f09b507 (diff)
downloadcoreboot-eb7e6b5c8160f5edfda1ac080ab77c1ba2c48306.tar.xz
amd/torpedo cimx/sb900: Fix include directory
Change-Id: Ie472092f8926231f4e1bd1fb12839b532b4ad158 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/23279 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src')
-rw-r--r--src/mainboard/amd/torpedo/BiosCallOuts.c2
-rw-r--r--src/southbridge/amd/cimx/sb900/gpio_oem.h9
2 files changed, 9 insertions, 2 deletions
diff --git a/src/mainboard/amd/torpedo/BiosCallOuts.c b/src/mainboard/amd/torpedo/BiosCallOuts.c
index 3e3d2520e2..7bdf71d9cf 100644
--- a/src/mainboard/amd/torpedo/BiosCallOuts.c
+++ b/src/mainboard/amd/torpedo/BiosCallOuts.c
@@ -18,7 +18,7 @@
#include <northbridge/amd/agesa/BiosCallOuts.h>
#include "Hudson-2.h"
#include <stdlib.h>
-#include <southbridge/amd/cimx/sb700/gpio_oem.h>
+#include <southbridge/amd/cimx/sb900/gpio_oem.h>
static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINTN Data, VOID *ConfigPtr);
static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *ConfigPtr);
diff --git a/src/southbridge/amd/cimx/sb900/gpio_oem.h b/src/southbridge/amd/cimx/sb900/gpio_oem.h
index b6bde9fdd5..f3ab5586a7 100644
--- a/src/southbridge/amd/cimx/sb900/gpio_oem.h
+++ b/src/southbridge/amd/cimx/sb900/gpio_oem.h
@@ -3,7 +3,7 @@
/* Hudson-2 ACPI PmIO Space Define */
#define SB_ACPI_BASE_ADDRESS 0x0400
-#define ACPI_MMIO_BASE ((u8 *)0xFED80000)
+#define VACPI_MMIO_BASE ((u8 *)0xFED80000)
#define SB_CFG_BASE 0x000 // DWORD
#define GPIO_BASE 0x100 // BYTE
#define SMI_BASE 0x200 // DWORD
@@ -43,4 +43,11 @@
#define Mmio32( BaseAddr, Register ) \
*Mmio32Ptr( BaseAddr, Register )
+#define SB_GPIO_REG01 1
+#define SB_GPIO_REG02 2
+#define SB_GPIO_REG15 15
+#define SB_GPIO_REG24 24
+#define SB_GPIO_REG25 25
+#define SB_GPIO_REG27 27
+
#endif