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authorMatt DeVillier <matt.devillier@puri.sm>2020-04-30 16:06:37 -0500
committerPatrick Georgi <pgeorgi@google.com>2020-05-02 17:07:39 +0000
commiteba32d217a7979dc1fa860c325351f86b98feb13 (patch)
tree2eb42d3133964f5f074b301827158868fd1cd9b9 /src
parent8c4ad5b4a56769327c3da80c57091f23c24016d7 (diff)
downloadcoreboot-eba32d217a7979dc1fa860c325351f86b98feb13.tar.xz
mb/purism/librem_bdw: Clean up 15v2 devicetree
The Librem 15v2 only uses SATA ports 0/1, so the DTLE settings for ports 2/3 have no consequence. Drop them to make overridetree conversion cleaner. Signed-off-by: Matt DeVillier <matt.devillier@puri.sm> Change-Id: I4145feecb389be90f317249426e58752c03aef76 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40914 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
-rw-r--r--src/mainboard/purism/librem_bdw/variants/librem15v2/devicetree.cb2
1 files changed, 0 insertions, 2 deletions
diff --git a/src/mainboard/purism/librem_bdw/variants/librem15v2/devicetree.cb b/src/mainboard/purism/librem_bdw/variants/librem15v2/devicetree.cb
index 32c3ed166f..cbd59bec8e 100644
--- a/src/mainboard/purism/librem_bdw/variants/librem15v2/devicetree.cb
+++ b/src/mainboard/purism/librem_bdw/variants/librem15v2/devicetree.cb
@@ -28,8 +28,6 @@ chip soc/intel/broadwell
# Port tuning for link stability
register "sata_port0_gen3_dtle" = "7"
register "sata_port1_gen3_dtle" = "9"
- register "sata_port2_gen3_dtle" = "9"
- register "sata_port3_gen3_dtle" = "7"
device cpu_cluster 0 on
device lapic 0 on end