diff options
| author | marxwang <marx.wang@intel.com> | 2017-12-11 14:57:49 +0800 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2017-12-13 15:42:28 +0000 |
| commit | ec5a947b44f1f2bd2bd90071df2617de608cd1c2 (patch) | |
| tree | 56b946e6fdd9c1248d7ad2d396c95ad6300bac43 /src | |
| parent | 1156c6656a3811bb57ede90521a0651f1f89065b (diff) | |
| download | coreboot-ec5a947b44f1f2bd2bd90071df2617de608cd1c2.tar.xz | |
soc/intel/skylake: make tcc_offset take effect
Currently, "tcc_offset" defined in devicetree is overwritten by
Intel FSP-S UPD "TccActivationOffset".
This patch will make "TccActivationOffset" refer to "tcc_offset".
TEST=check if MSR (0x1a2[29:24]) value is updated with "tcc_offset"
by iotools (rdmsr 0 0x1a2).
Change-Id: Ibc6f33bea19a1d59bc7e407815210942b38f0702
Signed-off-by: marxwang <marx.wang@intel.com>
Reviewed-on: https://review.coreboot.org/22818
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/intel/skylake/chip_fsp20.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c index f4060b2d99..2df013f563 100644 --- a/src/soc/intel/skylake/chip_fsp20.c +++ b/src/soc/intel/skylake/chip_fsp20.c @@ -290,6 +290,9 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) /* Enable/Disable EIST */ tconfig->Eist = config->eist_enable; + /* Set TccActivationOffset */ + tconfig->TccActivationOffset = config->tcc_offset; + soc_irq_settings(params); } |