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authorArthur Heymans <arthur@aheymans.xyz>2017-10-17 22:13:43 +0200
committerMartin Roth <martinroth@google.com>2017-11-23 04:59:26 +0000
commitf1c8ede1a5bcf26f938b3f5a8cfefa8acd156505 (patch)
tree8ca85c50eab6eb4f2fb79950273d4fffb2136169 /src
parenta35ad0e6ee7826dc1f171291116f306099c99e72 (diff)
downloadcoreboot-f1c8ede1a5bcf26f938b3f5a8cfefa8acd156505.tar.xz
sb/intel/i82801ix: fetch initial timestamp in bootblock
TESTED on Thinkpad x200 Change-Id: I3cd286709f8734793dc6ae303215433eff29d25b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/22077 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src')
-rw-r--r--src/mainboard/lenovo/t400/romstage.c2
-rw-r--r--src/mainboard/lenovo/x200/romstage.c2
-rw-r--r--src/mainboard/roda/rk9/romstage.c2
-rw-r--r--src/southbridge/intel/i82801ix/bootblock.c14
-rw-r--r--src/southbridge/intel/i82801ix/early_init.c11
5 files changed, 28 insertions, 3 deletions
diff --git a/src/mainboard/lenovo/t400/romstage.c b/src/mainboard/lenovo/t400/romstage.c
index f5d5dd1597..fd3544eb54 100644
--- a/src/mainboard/lenovo/t400/romstage.c
+++ b/src/mainboard/lenovo/t400/romstage.c
@@ -70,7 +70,7 @@ void mainboard_romstage_entry(unsigned long bist)
int cbmem_initted;
u16 reg16;
- timestamp_init(timestamp_get());
+ timestamp_init(get_initial_timestamp());
timestamp_add_now(TS_START_ROMSTAGE);
/* basic northbridge setup, including MMCONF BAR */
diff --git a/src/mainboard/lenovo/x200/romstage.c b/src/mainboard/lenovo/x200/romstage.c
index e3f4686250..d8ed0391e1 100644
--- a/src/mainboard/lenovo/x200/romstage.c
+++ b/src/mainboard/lenovo/x200/romstage.c
@@ -59,7 +59,7 @@ void mainboard_romstage_entry(unsigned long bist)
int cbmem_initted;
u16 reg16;
- timestamp_init(timestamp_get());
+ timestamp_init(get_initial_timestamp());
timestamp_add_now(TS_START_ROMSTAGE);
/* basic northbridge setup, including MMCONF BAR */
diff --git a/src/mainboard/roda/rk9/romstage.c b/src/mainboard/roda/rk9/romstage.c
index 9a8e34b18b..65ff0f8a84 100644
--- a/src/mainboard/roda/rk9/romstage.c
+++ b/src/mainboard/roda/rk9/romstage.c
@@ -125,7 +125,7 @@ void mainboard_romstage_entry(unsigned long bist)
int cbmem_initted;
u16 reg16;
- timestamp_init(timestamp_get());
+ timestamp_init(get_initial_timestamp());
timestamp_add_now(TS_START_ROMSTAGE);
/* basic northbridge setup, including MMCONF BAR */
diff --git a/src/southbridge/intel/i82801ix/bootblock.c b/src/southbridge/intel/i82801ix/bootblock.c
index 6252712eba..bb025b0eae 100644
--- a/src/southbridge/intel/i82801ix/bootblock.c
+++ b/src/southbridge/intel/i82801ix/bootblock.c
@@ -14,6 +14,19 @@
*/
#include <arch/io.h>
+#include <cpu/x86/tsc.h>
+
+static void store_initial_timestamp(void)
+{
+ /*
+ * We have two 32bit scratchpad registers available:
+ * D0:F0 0xdc (SKPAD)
+ * D31:F2 0xd0 (SATA SP)
+ */
+ tsc_t tsc = rdtsc();
+ pci_write_config32(PCI_DEV(0, 0x00, 0), 0xdc, tsc.lo);
+ pci_write_config32(PCI_DEV(0, 0x1f, 2), 0xd0, tsc.hi);
+}
static void enable_spi_prefetch(void)
{
@@ -30,5 +43,6 @@ static void enable_spi_prefetch(void)
static void bootblock_southbridge_init(void)
{
+ store_initial_timestamp();
enable_spi_prefetch();
}
diff --git a/src/southbridge/intel/i82801ix/early_init.c b/src/southbridge/intel/i82801ix/early_init.c
index c40f9b73ea..7c4dafaef6 100644
--- a/src/southbridge/intel/i82801ix/early_init.c
+++ b/src/southbridge/intel/i82801ix/early_init.c
@@ -15,8 +15,19 @@
*/
#include <arch/io.h>
+#include <timestamp.h>
+#include <cpu/x86/tsc.h>
#include "i82801ix.h"
+uint64_t get_initial_timestamp(void)
+{
+ tsc_t base_time = {
+ .lo = pci_read_config32(PCI_DEV(0, 0x00, 0), 0xdc),
+ .hi = pci_read_config32(PCI_DEV(0, 0x1f, 2), 0xd0)
+ };
+ return tsc_to_uint64(base_time);
+}
+
void i82801ix_early_init(void)
{
const pci_devfn_t d31f0 = PCI_DEV(0, 0x1f, 0);